公开(公告)号：US20250015147A1

公开(公告)日：2025-01-09

申请号：US18762960

申请日：2024-07-03

Applicant: Renesas Electronics Corporation

Inventor： Yuto OMIZU ,  Yu NAGAHAMA

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The insulating film IF1 is retracted so that the position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. An embedded insulating film EF1 is formed to cover the field plate electrode FP and the insulating film IF1. The embedded insulating film EF1 is retracted so that the position of the upper surface of the embedded insulating film EF1 is lower than the position of the upper surface of the field plate electrode FP. A gate insulating film GI is formed inside the trench TR, and an insulating film IF2 is formed to cover the field plate electrode FP. A gate electrode is formed on the field plate electrode FP via the insulating film IF2.

公开(公告)号：US20250040222A1

公开(公告)日：2025-01-30

申请号：US18772473

申请日：2024-07-15

Applicant: Renesas Electronics Corporation

Inventor： Yu NAGAHAMA

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: The reliability of the semiconductor device is improved. A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The other part of the field plate electrode FP is selectively retracted toward the bottom of the trench TR so that a part of the field plate electrode FP remains as a lead-out part FPa. A silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP by thermal oxidation. The insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB and the silicon oxide film OX1 are removed, and the insulating film IF1 is retracted so that its upper surface position is lower than the upper surface position of the field plate electrode FP.

公开(公告)号：US20240136410A1

公开(公告)日：2024-04-25

申请号：US18449769

申请日：2023-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yu NAGAHAMA ,  Yuya ABIKO

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/28229 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734

Abstract: A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.

公开(公告)号：US20240234517A9

公开(公告)日：2024-07-11

申请号：US18449769

申请日：2023-08-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yu NAGAHAMA ,  Yuya ABIKO

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/28229 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734

Abstract: A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.

公开(公告)号：US20230178646A1

公开(公告)日：2023-06-08

申请号：US17954859

申请日：2022-09-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yu NAGAHAMA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/7813 ,  H01L29/401 ,  H01L29/66727 ,  H01L29/66734

Abstract: A plurality of first trenches is formed in a cell region and a second trench is formed in an outer peripheral region. A gate electrode and a first field plate electrode are formed in each of the plurality of first trenches, and a second field plate electrode is formed in the second trench. For example, in a drift region formed in the outer peripheral region, a p-type column region is formed in a portion sandwiched, in a Y direction, by a portion, which is located between two of the plurality of first trenches arranged next to each other, and the second trench.