公开(公告)号：US20240274692A1

公开(公告)日：2024-08-15

申请号：US18522040

申请日：2023-11-28

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/66734 ,  H01L21/32135 ,  H01L29/401 ,  H01L29/407

Abstract: Reliability of a semiconductor device is improved. A field plate electrode is formed on an insulating film inside a trench. Next, by an isotropic etching process to the insulating film, the insulating film is thinned, and an upper portion of the field plate electrode is exposed from the insulating film. Next, an isotropic etching process (chemical dry etching process) is performed to the field plate electrode exposed from the insulating film. In this manner, a corner of the upper portion of the field plate electrode is chamfered or rounded, and therefore, a concentration of electric field at the upper portion of the field plate electrode can be moderated.

公开(公告)号：US20240304680A1

公开(公告)日：2024-09-12

申请号：US18437947

申请日：2024-02-09

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MARUYAMA ,  Tomoki AYANO ,  Yuya ABIKO

IPC: H01L29/40 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L29/407 ,  H01L29/4236

Abstract: A field plate electrode is formed in an inside of a trench via a first insulating film. Another part of the field plate electrode is selectively removed such that part of the field plate electrode is left as a lead portion. After the first insulating film is recessed, a protective film is formed on the first insulating film. A gate insulating film is formed in the inside of the trench, and a second insulating film is formed so as to cover the field plate electrode. A conductive film is formed on the gate insulating, second insulating film and protective films. A gate electrode is formed on the field plate electrode by removing the conductive film located in an outside of the trench. At this time, the conductive film formed on each of the protective film and the second insulating film, which are in contact with the lead portion, is removed.

公开(公告)号：US20240136410A1

公开(公告)日：2024-04-25

申请号：US18449769

申请日：2023-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yu NAGAHAMA ,  Yuya ABIKO

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/28229 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734

Abstract: A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.

公开(公告)号：US20180240905A1

公开(公告)日：2018-08-23

申请号：US15946060

申请日：2018-04-05

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Tetsuya IIDA ,  Akio ICHIMURA ,  Yuya ABIKO

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

公开(公告)号：US20140284705A1

公开(公告)日：2014-09-25

申请号：US14300327

申请日：2014-06-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi EGUCHI ,  Yuya ABIKO ,  Junichi KOGURE

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

Abstract translation: 在具有超结结构的漂移区域的超结功率MOSFET的制造步骤中，在形成超结结构之后，通常进行体区等的引入和与其相关的热处理。 然而，在其过程中，包含在超结结构中的每个P型列区域等中的掺杂剂被扩散以产生散射掺杂剂分布。 这导致了当在漏极和源极之间施加反向偏置电压和导通电阻增加时诸如击穿电压劣化的问题。 根据本发明，在制造硅基垂直平面功率MOSFET的方法中，通过选择性外延生长形成形成沟道区的体区。

公开(公告)号：US20230420556A1

公开(公告)日：2023-12-28

申请号：US18179731

申请日：2023-03-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuya ABIKO ,  Takahiro MARUYAMA

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/401

Abstract: An improved power MOSFET of a split gate structure including a gate electrode and a field plate electrode in a trench is disclosed. The improved power MOSFET includes a field plate electrode FP formed at a lower portion of a trench TR and a gate electrode GE formed an upper portion of the trench TR. The field plate electrode FP further includes a contact portion FPa which is formed at the upper portion of the trench TR to provide a source potential. The gate electrode GE further includes a connecting portion GEa at the both sides of the contact portion FPa in the trench TR. The connecting portion GEa electrically connects between one portion of the gate electrode GE at a region 2A side and the other portion of the gate electrode GE at a region 2A′ side.

公开(公告)号：US20180286952A1

公开(公告)日：2018-10-04

申请号：US15888944

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Natsuo YAMAGUCHI ,  Satoshi EGUCHI

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L21/265 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L21/308 ,  H01L29/66

Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

公开(公告)号：US20180158910A1

公开(公告)日：2018-06-07

申请号：US15869023

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Akio ICHIMURA ,  Natsuo YAMAGUCHI ,  Tetsuya IIDA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L21/38 ,  H01L21/76237 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

公开(公告)号：US20160268369A1

公开(公告)日：2016-09-15

申请号：US14968004

申请日：2015-12-14

Applicant: Renesas Electronics Corporation

Inventor： Akio ICHIMURA ,  Satoshi EGUCHI ,  Tetsuya IIDA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract translation: 形成具有高纵横比的超结结构。 外延层使用沟槽填充工艺分层地形成，并且当已经形成每个层时，在该层中形成沟槽。 例如，当已经形成第一外延层时，在外延层中形成第一沟槽。 随后，当已经形成第二外延层时，在外延层中形成第二沟槽。 随后，当形成第三外延层时，在第三外延层中形成第三沟槽。

公开(公告)号：US20240234517A9

公开(公告)日：2024-07-11

申请号：US18449769

申请日：2023-08-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yu NAGAHAMA ,  Yuya ABIKO

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/28229 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734

Abstract: A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.