公开(公告)号：US20230111142A1

公开(公告)日：2023-04-13

申请号：US17886049

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Yuta NABUCHI ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a plurality of unit cells. Each of the plurality of unit cells has a pair of column regions, a pair of trenches formed between the pair of column regions in the X direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. The two unit cells adjacent in the X direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region. Here, a distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is different from a distance between the pair of trenches in the one unit cell.

公开(公告)号：US20240395878A1

公开(公告)日：2024-11-28

申请号：US18630051

申请日：2024-04-09

Applicant: Renesas Electronics Corporation

Inventor： Yuta NABUCHI ,  Akihiro SHIMOMURA

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A trench TR1 and a trench TR2 are formed in a semiconductor substrate SUB so as to reach a predetermined depth from the upper surface (TS) of the semiconductor substrate SUB. A field plate electrode FP is formed at a lower portion of the trench TR1, and a gate electrode GE1 is formed at an upper portion of the trench TR1. A gate electrode GE2 is formed inside the trench TR2. The depth of the trench TR1 is deeper than the depth of the trench TR2. The trench TR1 extends in the Y direction, and the trench TR2 extends in the X direction. The trench TR1 and the trench TR2 are in communication with each other. The gate electrode GE1 and the gate electrode GE2 are integrated with each other.

公开(公告)号：US20230118274A1

公开(公告)日：2023-04-20

申请号：US17887156

申请日：2022-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Katsumi EIKYU ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

Abstract: A semiconductor device includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region, a body region, a source region, a pair of first column regions, and a gate electrode formed in a trench with a gate insulating film interposed therebetween. A well region is formed on a surface of the drift region in the outer peripheral region. A second column region is formed in the drift region below the well region and extends in Y and X directions so as to surround the cell region. The well region is connected to the body region, and the second column region is connected to the well region.

公开(公告)号：US20230352521A1

公开(公告)日：2023-11-02

申请号：US18152574

申请日：2023-01-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Akihiro SHIMOMURA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/7813 ,  H01L29/0696 ,  H01L29/66734

Abstract: An improved power MOSFET having a super junction structure is disclosed. The improved power MOSFET includes a plurality of unit cells UC, and each of the plurality of unit cells UC includes a column region PC1, a column region PC2, a pair of trenches TR formed between the column regions PC1 and PC2 in the X-direction and a pair of gate electrodes GE formed in the pair of trenches TR via gate insulating films (GI). The pair of trenches TR and the pair of gate-electrodes GE extend in Y-direction in a plan view. A plurality of column regions PC1 are formed so as to be spaced apart from one another along the Y-direction, and a width(L1) of the column region PC1 in the Y direction is wider than a width(L2) of the column region PC1 in the X direction.

公开(公告)号：US20230112550A1

公开(公告)日：2023-04-13

申请号：US17886073

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Hiroshi YANAGIGAWA ,  Katsumi EIKYU ,  Atsushi SAKAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/266

Abstract: A semiconductor device and a method of manufacturing the same capable of ensuring a sufficient breakdown voltage near a terminal end portion of a cell portion are provided. The cell portion includes a first cell column region and a second cell column region adjacent to each other, and a first cell trench gate and a second cell trench gate arranged between the first cell column region and the second cell column region. An outer peripheral portion includes an outer peripheral trench gate connected to an end portion of each of the first cell trench gate and the second cell trench gate, and a first outer peripheral column region arranged on the cell portion side with respect to the outer peripheral trench gate and extended across the first cell trench gate and the second cell trench gate in plan view.