公开(公告)号：US20240204098A1

公开(公告)日：2024-06-20

申请号：US18592332

申请日：2024-02-29

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20240055301A1

公开(公告)日：2024-02-15

申请号：US18336203

申请日：2023-06-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yudai HIGA ,  Atsushi SAKAI ,  Yotaro GOTO

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L27/088 ,  H01L21/823475

Abstract: A semiconductor device includes a cell region in which MISFETs are formed, and a peripheral region surrounding the cell region in plan view. In the cell region and the peripheral region, an n-type impurity region is formed in a semiconductor substrate. In the semiconductor substrate, an element isolation portion, a p-type impurity region, and an n-type impurity region are formed in the peripheral region so as to surround the cell region in plan view. A p-type impurity region and an n-type impurity region are formed in the semiconductor substrate in the cell region so as to contact the impurity region. The element isolation portion is located in the impurity region and is spaced apart from a junction interface between the impurity region and the impurity region.

公开(公告)号：US20210074816A1

公开(公告)日：2021-03-11

申请号：US16996351

申请日：2020-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20240290881A1

公开(公告)日：2024-08-29

申请号：US18638883

申请日：2024-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0274 ,  H01L29/0696 ,  H01L29/45 ,  H01L29/4916

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20230118274A1

公开(公告)日：2023-04-20

申请号：US17887156

申请日：2022-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Katsumi EIKYU ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

Abstract: A semiconductor device includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region, a body region, a source region, a pair of first column regions, and a gate electrode formed in a trench with a gate insulating film interposed therebetween. A well region is formed on a surface of the drift region in the outer peripheral region. A second column region is formed in the drift region below the well region and extends in Y and X directions so as to surround the cell region. The well region is connected to the body region, and the second column region is connected to the well region.

公开(公告)号：US20210217888A1

公开(公告)日：2021-07-15

申请号：US17216136

申请日：2021-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20230335635A1

公开(公告)日：2023-10-19

申请号：US17722788

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Yotaro GOTO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

公开(公告)号：US20230111142A1

公开(公告)日：2023-04-13

申请号：US17886049

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Yuta NABUCHI ,  Atsushi SAKAI ,  Akihiro SHIMOMURA ,  Satoru TOKUDA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a plurality of unit cells. Each of the plurality of unit cells has a pair of column regions, a pair of trenches formed between the pair of column regions in the X direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. The two unit cells adjacent in the X direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region. Here, a distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is different from a distance between the pair of trenches in the one unit cell.

公开(公告)号：US20190067470A1

公开(公告)日：2019-02-28

申请号：US16036489

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Hiroki FUJII ,  Atsushi SAKAI ,  Takahiro MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.

公开(公告)号：US20160163897A1

公开(公告)日：2016-06-09

申请号：US14948190

申请日：2015-11-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L31/0352 ,  H01L31/103 ,  H01L27/146

CPC classification number: H01L31/03529 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/103 ,  Y02E10/50

Abstract: To provide an imaging device equipped with a photodiode, which is capable of enhancing both of a capacity and sensitivity.In an area of a P-type well in which a photodiode is formed, a P-type impurity region is formed from the surface of the P-type well to a predetermined depth. Further, an N-type impurity region is formed to extend to a deeper position. N-type impurity regions and P-type impurity regions respectively extending in a gate width direction from a lower part of the N-type impurity region to a deeper position so as to contact the N-type impurity region are alternately arranged in a plural form along a gate length direction in a form to contact each other.

Abstract translation: 提供配备有光电二极管的成像装置，其能够增强容量和灵敏度。 在其中形成光电二极管的P型阱的区域中，从P型阱的表面到预定深度形成P型杂质区。 此外，形成N型杂质区域以延伸到更深的位置。 分别从N型杂质区域的下部向栅极宽度方向延伸以与N型杂质区域接触的较深位置的N型杂质区域和P型杂质区域以多种形式交替排列 沿着栅极长度方向以彼此接触的形式。