公开(公告)号：US20190043983A1

公开(公告)日：2019-02-07

申请号：US16028146

申请日：2018-07-05

Applicant: Renesas Electronics Corporation

Inventor： Taro MORIYA ,  Hiroyoshi KUDOU ,  Hiroshi YANAGIGAWA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/763 ,  H01L27/06 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, and a first contact plug. The semiconductor substrate includes a first surface and a second surface. Over the semiconductor substrate, a source region, a drain region, a drift region, and a body region are formed. A first trench in which the gate electrode is buried is formed in the first surface. The first surface includes an effective region and a peripheral region. The first trench extends from the peripheral region over the effective region along a first direction. The gate electrode includes a portion opposed to and insulated from the body region sandwiched between the source region and the drift region. In the peripheral region, the first contact plug is electrically coupled to the gate electrode buried in the first trench such that its longer side is along the first direction when seen in a plan view.

公开(公告)号：US20230275069A1

公开(公告)日：2023-08-31

申请号：US18059583

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA ,  Yasutaka NAKASHIBA ,  Toshiyuki HATA

IPC: H01L25/065 ,  H01L23/495 ,  H01L23/498 ,  H01L23/482

CPC classification number: H01L25/0657 ,  H01L23/4828 ,  H01L23/49572 ,  H01L23/49844

Abstract: A semiconductor device includes a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed on a first front surface of the first semiconductor chip, and a first drain electrode is formed on a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed on a second front surface of the second semiconductor chip, and a second drain electrode is formed on a second back surface of the second semiconductor chip. The first back surface and the second back surface are faced to each other such that the first drain electrode and the second drain electrode are in contact with each other via a conductive tape.

公开(公告)号：US20230112550A1

公开(公告)日：2023-04-13

申请号：US17886073

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Hiroshi YANAGIGAWA ,  Katsumi EIKYU ,  Atsushi SAKAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/266

Abstract: A semiconductor device and a method of manufacturing the same capable of ensuring a sufficient breakdown voltage near a terminal end portion of a cell portion are provided. The cell portion includes a first cell column region and a second cell column region adjacent to each other, and a first cell trench gate and a second cell trench gate arranged between the first cell column region and the second cell column region. An outer peripheral portion includes an outer peripheral trench gate connected to an end portion of each of the first cell trench gate and the second cell trench gate, and a first outer peripheral column region arranged on the cell portion side with respect to the outer peripheral trench gate and extended across the first cell trench gate and the second cell trench gate in plan view.

公开(公告)号：US20240363747A1

公开(公告)日：2024-10-31

申请号：US18603396

申请日：2024-03-13

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/1095

Abstract: The semiconductor device includes a pair of gate-electrodes GE formed inside the pair of trenches TR via an gate insulating film (GI), respectively. The pair of column regions PC are spaced apart from each other in the Y-direction. The pair of trenches TR are provided apart from each other in the Y direction, are provided between the pair of column regions PC in the Y direction, and extend in the X direction. The ends of the pair of trenches TR in the X direction are connected to each other by a connecting portion TRa extending in the Y direction. The connection portion TRa is integrated with the pair of trenches TR. The pair of column regions PC extend in the X direction along the pair of trenches TR, and extend in the X direction toward the outer edge of the semiconductor substrate beyond the connection portion TRa.

公开(公告)号：US20240162222A1

公开(公告)日：2024-05-16

申请号：US18509870

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L28/20 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

Abstract: Reliability of a semiconductor device is improved and reduction in yield is reduced. In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. In the semiconductor substrate SUB, a body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. The source region NS, the n-type source region, the n-type drain region, the p-type source region and the p-type drain region are subjected to heat treatment. After heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB.

公开(公告)号：US20240162143A1

公开(公告)日：2024-05-16

申请号：US18509874

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76885 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a semiconductor substrate SUB, a trench TR is formed.
A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. An interlayer insulating film IL1 is formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL1, a hole CH1 is formed in the source region NS and in the body region PB. Holes CH3 are formed in the interlayer insulating film IL1 so as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.

公开(公告)号：US20240006344A1

公开(公告)日：2024-01-04

申请号：US18330648

申请日：2023-06-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Toshiyuki HATA ,  Hiroshi YANAGIGAWA ,  Tomohisa SEKIGUCHI

IPC: H01L23/00 ,  H01L23/58 ,  H01L29/78 ,  H01L21/78 ,  H01L21/306

CPC classification number: H01L23/562 ,  H01L24/32 ,  H01L23/585 ,  H01L29/7813 ,  H01L21/78 ,  H01L21/30604 ,  H01L2224/32225

Abstract: A semiconductor device includes a chip mounting portion and a semiconductor chip provided on the chip mounting portion via a conductive adhesive material. Here, a planar shape of the semiconductor chip is a quadrangular shape. Also, in plan view, a plurality of thin portions is formed at a plurality of corner portions of the semiconductor chip, respectively. Also, the plurality of thin portions respectively formed at the plurality of corner portions of the semiconductor chip is spaced apart from each other. Further, thickness of each of the plurality of thin portions is smaller than a thickness of the semiconductor chip other than the plurality of the thin portions.

公开(公告)号：US20250015175A1

公开(公告)日：2025-01-09

申请号：US18890208

申请日：2024-09-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori KAYA ,  Katsumi EIKYU ,  Akihiro SHIMOMURA ,  Hiroshi YANAGIGAWA ,  Kazuhisa MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

公开(公告)号：US20210159331A1

公开(公告)日：2021-05-27

申请号：US17095241

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Satoru TOKUDA ,  Ryuuji UMEMOTO ,  Katsumi EIKYU ,  Hiroshi YANAGIGAWA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.

公开(公告)号：US20170279446A1

公开(公告)日：2017-09-28

申请号：US15622370

申请日：2017-06-14

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA

IPC: H03K17/687 ,  H03K17/081

CPC classification number: H03K17/687 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/181 ,  H03K17/08104 ,  H03K2217/0063 ,  H03K2217/0072 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present invention is provided to easily manufacture an IPD as any of a high-side switch and a low-side switch. A level shifting circuit is coupled to an input terminal, a first terminal, and a grounding terminal. Drive power of the level shifting circuit is supplied from the first terminal. An output signal of the level shifting circuit is input to a driver circuit. The driver circuit is coupled to the first terminal and a second terminal. Drive power of the driver circuit is supplied from the first terminal. A transistor has a gate electrode coupled to the driver circuit, a source coupled to the second terminal, and a drain coupled to a third terminal.