公开(公告)号：US11876093B2

公开(公告)日：2024-01-16

申请号：US17142154

申请日：2021-01-05

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chih-Feng Huang ,  Lung-Sheng Lin

IPC: H01L27/07 ,  H01L29/739 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/872

CPC classification number: H01L27/0722 ,  H01L21/8249 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/872

Abstract: A power device which is formed on a semiconductor substrate includes: plural lateral insulated gate bipolar transistors (LIGBTs) and a forward conductive unit. The plural LIGBTs are connected in parallel to each other. The forward conductive unit is connected in parallel to the plural LIGBTs. The forward conductive unit consists of a PN diode and a Schottky diode connected in parallel to each other. The PN diode and the Schottky diode share a same N-type region, a reverse terminal, an N-type extension region, an field oxide region, a gate, and a P-type well in an epitaxial layer. The N-type region and the P-type well form a PN junction, wherein the PN junction has a staggered comb-teeth interface from top view. A metal line extends on the staggered comb-teeth interface and alternatingly contacts the N-type region and the P-type well.

公开(公告)号：US20220406693A1

公开(公告)日：2022-12-22

申请号：US17736445

申请日：2022-05-04

Applicant: Richtek Technology Corporation

Inventor： Lung-Sheng Lin ,  Chih-Feng Huang

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: An intelligent power module includes: an encapsulating material structure; a lead frame which is at least partially encapsulated inside the encapsulating material structure, wherein all portions of the lead frame encapsulated inside the encapsulating material structure are at a same planar level; and a heat dissipation structure, which is connected to the lead frame.

公开(公告)号：US20210305242A1

公开(公告)日：2021-09-30

申请号：US17142154

申请日：2021-01-05

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chih-Feng Huang ,  Lung-Sheng Lin

IPC: H01L27/07 ,  H01L29/739 ,  H01L29/66 ,  H01L29/872 ,  H01L21/8249

Abstract: A power device which is formed on a semiconductor substrate includes: plural lateral insulated gate bipolar transistors (LIGBTs) and a forward conductive unit. The plural LIGBTs are connected in parallel to each other. The forward conductive unit is connected in parallel to the plural LIGBTs. The forward conductive unit consists of a PN diode and a Schottky diode connected in parallel to each other. The PN diode and the Schottky diode share a same N-type region, a reverse terminal, an N-type extension region, an field oxide region, a gate, and a P-type well in an epitaxial layer. The N-type region and the P-type well form a PN junction, wherein the PN junction has a staggered comb-teeth interface from top view. A metal line extends on the staggered comb-teeth interface and alternatingly contacts the N-type region and the P-type well.

公开(公告)号：US09048732B2

公开(公告)日：2015-06-02

申请号：US14294789

申请日：2014-06-03

Applicant: Richtek Technology Corporation

Inventor： Yi-Wei Lee ,  Chih-Feng Huang ,  Kuo-Chin Chiu

IPC: H02M7/217 ,  H02M7/537 ,  H01L29/808 ,  H02M7/00 ,  H01L29/06

CPC classification number: H02M7/217 ,  H01L29/0692 ,  H01L29/808 ,  H02M7/003 ,  H02M7/537

Abstract: A control circuit for an AC-DC power converter includes a junction field effect transistor (JFET), a first resistor, a second resistor, and a third resistor. The JFET includes a substrate, a drain, a source, a gate, a first oxide layer, and a second oxide layer. The first oxide layer is attached to a region located between the drain and the gate of the JFET, and the second oxide layer is not attached to a region located between the drain and the gate of the JFET. The first resistor is positioned on the first oxide layer, and the second resistor and the third resistor are positioned on the second oxide layer. When the JFET and the first resistor receive an input power signal, the first, the second, and the third resistors divide the input power signal, and prevent from the breakdown of the first oxide layer and the second oxide layer.

Abstract translation: 用于AC-DC电力转换器的控制电路包括结型场效应晶体管（JFET），第一电阻器，第二电阻器和第三电阻器。 JFET包括衬底，漏极，源极，栅极，第一氧化物层和第二氧化物层。 第一氧化物层附接到位于JFET的漏极和栅极之间的区域，并且第二氧化物层未附接到位于JFET的漏极和栅极之间的区域。 第一电阻器位于第一氧化物层上，第二电阻器和第三电阻器位于第二氧化物层上。 当JFET和第一电阻器接收输入功率信号时，第一，第二和第三电阻器分割输入功率信号，并防止第一氧化物层和第二氧化物层的击穿。

公开(公告)号：US11646364B2

公开(公告)日：2023-05-09

申请号：US17187540

申请日：2021-02-26

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chih-Feng Huang ,  Lung-Sheng Lin

IPC: H01L29/739 ,  H01L29/66 ,  H01L27/07 ,  H01L27/02

CPC classification number: H01L29/7393 ,  H01L27/0248 ,  H01L27/0783 ,  H01L29/66325

Abstract: A power device which is formed on a semiconductor substrate includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode and a clamp diode. The PN diode is connected in parallel to the LIGBT. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a drain and a gate of the LIGBT, to clamp a gate voltage applied to the gate not to be higher than a predetermined voltage threshold.

公开(公告)号：US20210305414A1

公开(公告)日：2021-09-30

申请号：US17187540

申请日：2021-02-26

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chih-Feng Huang ,  Lung-Sheng Lin

IPC: H01L29/739 ,  H01L27/02 ,  H01L27/07 ,  H01L29/66

Abstract: A power device which is formed on a semiconductor substrate includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode and a clamp diode. The PN diode is connected in parallel to the LIGBT. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a drain and a gate of the LIGBT, to clamp a gate voltage applied to the gate not to be higher than a predetermined voltage threshold.

公开(公告)号：US20220406691A1

公开(公告)日：2022-12-22

申请号：US17561968

申请日：2021-12-26

Applicant: Richtek Technology Corporation

Inventor： Lung-Sheng Lin ,  Chih-Feng Huang

IPC: H01L23/495 ,  H01L23/31

Abstract: An intelligent power module, which includes: a lead frame; a plurality of signal processing chips, disposed on the lead frame; at least one bridge die, configured to operably transmit signals among the signal processing chips; and a package structure, encapsulating the lead frame, the signal processing chips and the bridge die.

公开(公告)号：US09084327B2

公开(公告)日：2015-07-14

申请号：US13789325

申请日：2013-03-07

Applicant: Richtek Technology Corporation

Inventor： Kuo-Chin Chiu ,  Chih-Feng Huang

IPC: H05B33/08

CPC classification number: H02M3/158 ,  G05F1/16 ,  G05F3/16 ,  H05B33/083 ,  H05B33/0851 ,  H05B33/0854

Abstract: A driver circuit for driving an LED array is disclosed. The LED array includes a first, a second, a third, a fourth LED device and a diode device. The second LED device is connected to the first LED device. The fourth LED device is connected to the third LED device. The diode device is connected between the second LED device and the third LED device. The driver circuit includes a first constant current regulator for coupling between the first and the second LED device; a second constant current regulator for coupling between the second and the third LED device; a third constant current regulator for coupling between the third and the fourth LED device; a fourth constant current regulator for coupling between the fourth LED device and a fixed-voltage terminal; and a control circuit coupled with the first, the second, the third, and the fourth constant current regulators.

Abstract translation: 公开了一种用于驱动LED阵列的驱动电路。 LED阵列包括第一，第二，第三，第四LED器件和二极管器件。 第二LED装置连接到第一LED装置。 第四LED装置连接到第三LED装置。 二极管器件连接在第二LED器件和第三LED器件之间。 驱动器电路包括用于在第一和第二LED器件之间耦合的第一恒流调节器; 用于耦合在所述第二和第三LED器件之间的第二恒流调节器; 用于耦合在第三和第四LED器件之间的第三恒流调节器; 用于在第四LED器件和固定电压端子之间耦合的第四恒流调节器; 以及与第一，第二，第三和第四恒定电流调节器耦合的控制电路。