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    Method for manufacturing semiconductor integrated circuit device
    2.
    发明授权
    Method for manufacturing semiconductor integrated circuit device 有权
    半导体集成电路器件的制造方法

    公开(公告)号：US06909133B2

    公开(公告)日：2005-06-21

    申请号：US10699690

    申请日：2003-11-04

    申请人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

    发明人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

    IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/108

    CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

    摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

    摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。

    Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
    3.
    发明授权
    Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array 失效
    具有4F方形存储单元阵列中堆叠电容器的自对准扩散源垂直晶体管

    公开(公告)号：US5929477A

    公开(公告)日：1999-07-27

    申请号：US792955

    申请日：1997-01-22

    申请人： Stuart McAllister Burns, Jr. ,  Hussein Ibrahim Hanafi ,  Jeffrey J. Welser ,  Waldemar Walter Kocon ,  Howard Leo Kalter

    发明人： Stuart McAllister Burns, Jr. ,  Hussein Ibrahim Hanafi ,  Jeffrey J. Welser ,  Waldemar Walter Kocon ,  Howard Leo Kalter

    IPC分类号： H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/108 ,  H01L29/76

    CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/10852

    摘要： A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.

    摘要翻译： 公开了一种密集堆叠的垂直半导体器件阵列，其上具有堆叠电容器的柱及其制造方法。 支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。 低掺杂区域是自对准的并且位于柱下方。 该阵列具有位线和字线行。 相邻位线的较低掺杂区域可以彼此隔离，而不增加单元尺寸，并允许维持约4F2的最小面积。 该阵列适用于Gbit DRAM应用，因为堆叠电容器不会增加阵列面积。 阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。 可以最初植入下部区域。 或者，下部区域在其形成之后可以在柱下方扩散。 在这种情况下，可以控制下部区域扩散以形成从下面的衬底分离的浮动柱，或者保持柱和衬底之间的接触。