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公开(公告)号：US06950841B2
公开(公告)日：2005-09-27
申请号：US09954760
申请日：2001-09-14
CPC分类号： G06F7/5235 , G06F1/0356 , G06F2101/10
摘要： In one embodiment, the invention is directed toward techniques for generating results in a logarithmic domain. The techniques may exploit properties of a logarithmic function to reduce the memory requirements needed to implement lookup tables. For example, the techniques may utilize non-uniform sampling over a logarithmic or logarithmic-like function to reduce the number of entries needed for a given lookup table. In particular, the techniques may involve separating a number into an exponent component and a mantissa component. Each of these different components can then be converted from a first domain to a second domain using different lookup tables.
摘要翻译： 在一个实施例中，本发明涉及用于在对数域中生成结果的技术。 这些技术可以利用对数函数的属性来减少实现查找表所需的内存要求。 例如，这些技术可以利用对数或类似对数的函数的非均匀采样来减少给定查找表所需的条目数。 特别地，这些技术可以包括将数字分成指数分量和尾数分量。 然后可以使用不同的查找表将这些不同组件中的每一个从第一域转换为第二域。
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公开(公告)号：US08626099B2
公开(公告)日：2014-01-07
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B1/06
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。
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公开(公告)号：US08615212B2
公开(公告)日：2013-12-24
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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公开(公告)号：US07076225B2
公开(公告)日：2006-07-11
申请号：US10034734
申请日：2001-12-21
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。
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公开(公告)号：US20110105070A1
公开(公告)日：2011-05-05
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。
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公开(公告)号：US20080014895A1
公开(公告)日：2008-01-17
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett Walker , Paul Peterzell , Raghu Challa , Matthew Severson , Arun Raghupathy , Gilbert Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett Walker , Paul Peterzell , Raghu Challa , Matthew Severson , Arun Raghupathy , Gilbert Sih
IPC分类号： H04B1/26
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译： 具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。 可以如本文所述有利地设计和定位DVGA。 可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。 在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。 一些或全部RF /模拟电路的控制可以通过串行总线提供。
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公开(公告)号：US09119165B2
公开(公告)日：2015-08-25
申请号：US13535626
申请日：2012-06-28
申请人： Norman Krasner , Arun Raghupathy
发明人： Norman Krasner , Arun Raghupathy
摘要： Embodiments describe determining position by selecting a set of digital pseudorandom sequences. The magnitudes of the cross-correlation between any two sequences of the chosen set are below a specified threshold. A subset of digital pseudorandom sequences are selected from the set such that the magnitudes of the autocorrelation function of each member of the subset, within a specified region adjacent to the peak of the autocorrelation function, are equal to or less than a prescribed value. Each transmitter transmits a positioning signal, and at least a portion of the positioning signal is modulated with at least one member of the subset. At least two transmitters of the plurality of transmitters modulate respective positioning signals with different members of the subset of digital pseudorandom sequences.
摘要翻译： 实施例描述了通过选择一组数字伪随机序列来确定位置。 所选集合的任何两个序列之间的互相关的幅度低于指定的阈值。 从集合中选择数字伪随机序列的子集，使得在与自相关函数的峰相邻的特定区域内的子集的每个成员的自相关函数的大小等于或小于规定值。 每个发射机发送定位信号，并且用该子集中的至少一个成员来调制定位信号的至少一部分。 多个发射机中的至少两个发射机利用数字伪随机序列子集的不同成员调制相应的定位信号。
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8.发明授权Mitigation circuitry generating cross correlation doppler/code LAG variable comparison value 有权产生互相关多普勒/代码LAG变量比较值的缓解电路公开(公告)号：US09036683B2
公开(公告)日：2015-05-19
申请号：US12719965
申请日：2010-03-09
IPC分类号： H04B1/00 , H04B1/7075 , G01S19/21
CPC分类号： G01S19/21 , H04B1/70755 , H04B2201/70715
摘要： A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes a correlator circuit (120) operable to correlate the signals with a selectable locally-issued PN code having a Doppler and a code lag to produce a peak, the correlator circuit (120) being subject to cross correlation with a distinct PN code carried by least one of the signals that can produce cross correlation; and a cross correlation circuit (370, 400) operable to generate a variable comparison value related to the cross correlation as a function of values representing a Doppler difference and a code lag difference between the locally-issued PN code and the distinct PN code, and to use the variable comparison value to reject the peak as invalid from cross correlation or to pass the peak as a valid received peak.
摘要翻译： 为不同信号强度的信号提供接收机（100），并用各自的伪随机噪声（PN）码进行调制。 接收器（100）包括相关器电路（120），其可操作以将信号与具有多普勒和码滞后的可选择本地发出的PN码相关以产生峰值，所述相关器电路（120）与 不同PN码携带的信号中至少有一个会产生互相关; 以及互相关电路（370,400），其可操作以根据表示本地发出的PN码和不同PN码之间的多普勒差和码滞差的值产生与互相关的可变比较值，以及 使用可变比较值将峰值从互相关中排除为无效，或将峰值作为有效接收峰值传递。
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公开(公告)号：US20130324154A1
公开(公告)日：2013-12-05
申请号：US13909977
申请日：2013-06-04
申请人： Arun Raghupathy , Ganesh Pattabiraman , Kumar Shubham , Henry Clark , Andrew Sendonaris , Steven J. Willhoff
发明人： Arun Raghupathy , Ganesh Pattabiraman , Kumar Shubham , Henry Clark , Andrew Sendonaris , Steven J. Willhoff
IPC分类号： H04W4/02
CPC分类号： G01S19/46 , G01S5/0236 , G01S19/10 , G01S19/42 , G01S19/52 , H04W4/02 , H04W4/025 , H04W64/00
摘要： Devices, systems, and methods for gathering, calculating and sending positioning information at a user device to one or more networks may be disclosed. In a first implementation the user device transforms pseudorange information relating to terrestrial beacons into GNSS pseudorange information. In a second implementation, the user device sends position information using GNSS information elements. In a third implementation, the user device sends position information using non-GNSS information elements.
摘要翻译： 可以公开用于在用户设备处收集，计算和发送定位信息到一个或多个网络的设备，系统和方法。 在第一实现中，用户设备将与陆地信标相关的伪距信息转换成GNSS伪距信息。 在第二实施例中，用户设备使用GNSS信息元素发送位置信息。 在第三实施方式中，用户设备使用非GNSS信息元素发送位置信息。
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公开(公告)号：US08130141B2
公开(公告)日：2012-03-06
申请号：US12557479
申请日：2009-09-10
IPC分类号： G01S19/46
CPC分类号： H04B1/7087 , G01S1/08 , G01S5/10 , G01S19/11 , G01S19/24 , G01S19/42 , G01S19/46 , H04B1/709 , H04B7/2618 , H04B2201/7073 , H04W4/02 , H04W56/005 , H04W72/005 , H04W72/0446 , H04W72/048
摘要： Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals.
摘要翻译： 描述了用于确定接收机的位置的系统和方法。 定位系统包括发射机网络，其包括广播定位信号的发射机。 该定位系统包括一个远程接收器，用于获取和跟踪定位信号和/或卫星信号。 卫星信号是基于卫星的定位系统的信号。 远程接收机的第一模式使用基于终端的定位，其中远程接收机使用定位信号和/或卫星信号来计算位置。 定位系统包括耦合到远程接收器的服务器。 远程接收机的第二操作模式包括基于网络的定位，其中服务器根据定位信号和/或卫星信号计算远程接收器的位置，其中远程接收器接收并向服务器传送定位信号和/或 卫星信号。
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