公开(公告)号：US20070011536A1

公开(公告)日：2007-01-11

申请号：US11157526

申请日：2005-06-21

申请人： Rahul Khanna ,  Mohan Kumar ,  Jay Nejedlo

发明人： Rahul Khanna ,  Mohan Kumar ,  Jay Nejedlo

IPC分类号： G01R31/28

CPC分类号： G06F11/27

摘要： Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

摘要翻译： 执行链接的训练，其中链路是计算机系统的两个设备之间的互连。 链接的内置自检（BIST）被执行。 将链接训练的结果与BIST的结果进行比较。 张贴链接的链接状态，其中链接状态至少部分地基于链接训练的结果和来自BIST的结果。

公开(公告)号：US07437643B2

公开(公告)日：2008-10-14

申请号：US11157526

申请日：2005-06-21

申请人： Rahul Khanna ,  Mohan J. Kumar ,  Jay Nejedlo

发明人： Rahul Khanna ,  Mohan J. Kumar ,  Jay Nejedlo

IPC分类号： G01R31/28

CPC分类号： G06F11/27

摘要： Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

摘要翻译： 执行链接的训练，其中链路是计算机系统的两个设备之间的互连。 链接的内置自检（BIST）被执行。 将链接训练的结果与BIST的结果进行比较。 张贴链接的链接状态，其中链接状态至少部分地基于链接训练的结果和来自BIST的结果。

公开(公告)号：US07155370B2

公开(公告)日：2006-12-26

申请号：US10393223

申请日：2003-03-20

申请人： Jay Nejedlo

发明人： Jay Nejedlo

IPC分类号： G06F15/00 ,  G01R31/00

CPC分类号： G06F11/27

摘要： A methodology for testing a computer system using multiple test units, each test unit being associated with its respective core function circuitry. The core circuitry and its respective test unit are located in a primary integrated circuit component of the computer system, such as a processor, memory, or chipset. The on-chip test units communicate with one another and with other parts of the system, to determine whether a specification of the computer system is satisfied, without requiring a processor core of the computer system to execute an operating system program for the computer system.

摘要翻译： 一种用于测试使用多个测试单元的计算机系统的方法，每个测试单元与其相应的核心功能电路相关联。 核心电路及其各自的测试单元位于计算机系统的主要集成电路部件中，例如处理器，存储器或芯片组。 片上测试单元彼此通信并与系统的其他部分通信，以确定计算机系统的规格是否满足，而不需要计算机系统的处理器核心来执行计算机系统的操作系统程序。

公开(公告)号：US20070073507A1

公开(公告)日：2007-03-29

申请号：US11465082

申请日：2006-08-16

申请人： James Chorn ,  Thomas Hudiburgh ,  Jay Nejedlo ,  Edward Simpson

发明人： James Chorn ,  Thomas Hudiburgh ,  Jay Nejedlo ,  Edward Simpson

IPC分类号： G01R27/28

CPC分类号： G01R31/31912 ,  G01R31/318314

摘要： A graphic user interface for configuring a test control program for a circuit. More particularly the circuit includes a built-in-self-test compatible device and has a test configuration. The device has an associated value. Moreover, the circuit, the device, and the value are defined in a circuit definition. The interface includes an object representing the circuit, an object representing the device, and an object representing the value. Furthermore, at least one of the objects is configured and adapted to allow a modification to the object and to reconfigure the test configuration program in response to the object modification. Also, the object is further configured and adapted to modify itself to reflect a modification of the circuit definition. More particularly, the device may be an IBIST compatible device having registers, ports and lanes of the ports. Methods of, and computer programs for, configuring test control programs are also provided.

摘要翻译： 用于配置电路测试控制程序的图形用户界面。 更具体地，该电路包括内置的自检测兼容设备并且具有测试配置。 设备具有相关联的值。 此外，电路，设备和值在电路定义中定义。 接口包括表示电路的对象，表示设备的对象以及表示该值的对象。 此外，至少一个对象被配置和适于允许修改对象并且响应于对象修改来重新配置测试配置程序。 此外，该对象被进一步配置并适于修改自身以反映电路定义的修改。 更具体地，该设备可以是具有端口的寄存器，端口和通道的IBIST兼容设备。 还提供了配置测试控制程序的方法和计算机程序。

公开(公告)号：US20050080581A1

公开(公告)日：2005-04-14

申请号：US10668817

申请日：2003-09-22

申请人： David Zimmerman ,  Jay Nejedlo

发明人： David Zimmerman ,  Jay Nejedlo

IPC分类号： G06F19/00 ,  G11C29/02 ,  G11C29/16

CPC分类号： G11C29/16 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/0401 ,  G11C2029/0405

摘要： In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

摘要翻译： 在一些实施例中，为具有存储器控制器逻辑的集成电路（IC）设备提供内置的自检逻辑，以产生访问存储器件的地址和命令信息。 驱动器电路采用内存控制器逻辑芯片。 驱动器电路具有分别耦合到片上信号焊盘的输出。 BIST逻辑耦合在驱动器电路和控制器逻辑之间。 BIST逻辑是在设备的正常操作模式下使用驱动器电路以速度传送由控制器逻辑产生的地址和命令信息。 此外，BIST逻辑能够在IC器件的测试操作模式下使用驱动器电路以速度传输测试符号，在此期间测试IC器件与另一器件之间的芯片到芯片的连接。 还描述和要求保护其他实施例。

公开(公告)号：US20070079199A1

公开(公告)日：2007-04-05

申请号：US11465080

申请日：2006-08-16

申请人： James Chorn ,  Thomas Hudiburgh ,  Jay Nejedlo ,  Edward Simpson ,  Walter Coldewey

发明人： James Chorn ,  Thomas Hudiburgh ,  Jay Nejedlo ,  Edward Simpson ,  Walter Coldewey

IPC分类号： G01R31/28

CPC分类号： G01R31/318583 ,  G01R31/31855

摘要： Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using a descriptive language including setting at least one default value associated with the device. The method also includes defining a scan path associated with the device, defining a netlist of the circuit, and configuring a test control program for the circuit. Additionally, the method includes changing the default value associated with the device. Testing the circuit after changing the value and using the test control program is also included wherein a portion of the test control program associated with the value remains substantially unmodified.

摘要翻译： 在包括至少一个内置自测兼容装置的电路上执行数据驱动测试的方法和装置。 在一个实施例中，该方法包括使用描述语言描述设备，包括设置与设备相关联的至少一个默认值。 该方法还包括定义与设备相关联的扫描路径，定义电路的网表，以及配置电路的测试控制程序。 此外，该方法包括更改与设备相关联的默认值。 还包括在更改值和使用测试控制程序之后测试电路，其中与该值相关联的测试控制程序的一部分基本上未被修改。

公开(公告)号：US07047458B2

公开(公告)日：2006-05-16

申请号：US10319517

申请日：2002-12-16

申请人： Jay Nejedlo ,  Sean R. Babcock

发明人： Jay Nejedlo ,  Sean R. Babcock

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G06F11/27 ,  G01R31/2853 ,  G01R31/31855 ,  G01R31/3187

摘要： A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

摘要翻译： 提供内置自检（IBIST）架构/方法来测试两个组件之间的互连（如总线）的功能。 该IBIST架构可以包括模式生成器和模式检查器。 模式检查器操作以将接收到的多个比特（对于模式生成器）与先前存储的多个比特进行比较。

公开(公告)号：US20060080058A1

公开(公告)日：2006-04-13

申请号：US11289186

申请日：2005-11-28

申请人： David Zimmerman ,  Jay Nejedlo

发明人： David Zimmerman ,  Jay Nejedlo

IPC分类号： G01R31/00

CPC分类号： G11C29/16 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/0401 ,  G11C2029/0405

摘要： In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.