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    Built-in self test for memory interconnect testing
    1.
    发明申请
    Built-in self test for memory interconnect testing 审中-公开
    内置自检内存互连测试

    公开(公告)号：US20050080581A1

    公开(公告)日：2005-04-14

    申请号：US10668817

    申请日：2003-09-22

    申请人： David Zimmerman ,  Jay Nejedlo

    发明人： David Zimmerman ,  Jay Nejedlo

    IPC分类号： G06F19/00 ,  G11C29/02 ,  G11C29/16

    CPC分类号： G11C29/16 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/0401 ,  G11C2029/0405

    摘要： In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

    摘要翻译： 在一些实施例中，为具有存储器控制器逻辑的集成电路（IC）设备提供内置的自检逻辑，以产生访问存储器件的地址和命令信息。 驱动器电路采用内存控制器逻辑芯片。 驱动器电路具有分别耦合到片上信号焊盘的输出。 BIST逻辑耦合在驱动器电路和控制器逻辑之间。 BIST逻辑是在设备的正常操作模式下使用驱动器电路以速度传送由控制器逻辑产生的地址和命令信息。 此外，BIST逻辑能够在IC器件的测试操作模式下使用驱动器电路以速度传输测试符号，在此期间测试IC器件与另一器件之间的芯片到芯片的连接。 还描述和要求保护其他实施例。

    Built-in self test for memory interconnect testing
    2.
    发明申请
    Built-in self test for memory interconnect testing 有权

    公开(公告)号：US20060080058A1

    公开(公告)日：2006-04-13

    申请号：US11289186

    申请日：2005-11-28

    申请人： David Zimmerman ,  Jay Nejedlo

    发明人： David Zimmerman ,  Jay Nejedlo

    IPC分类号： G01R31/00

    CPC分类号： G11C29/16 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/0401 ,  G11C2029/0405

    摘要： In some embodiments, built-in self-test logic is provided for an integrated circuit (IC) device having memory controller logic to generate address and command information for accessing a memory device. Driver circuits are on-chip with the memory controller logic. The driver circuits have outputs that are coupled to on-chip signal pads, respectively. The BIST logic is coupled between the driver circuits and the controller logic. The BIST logic is to transmit, at speed, address and command information that has been generated by the controller logic using the driver circuits in a normal mode of operation for the device. In addition, the BIST logic is able to transmit, at speed, test symbols using the driver circuits in a test mode of operation for the IC device, during which a chip-to-chip connection between the IC device and another device is tested. Other embodiments are also described and claimed.

    Memory channel self test
    4.
    发明申请
    Memory channel self test 有权
    内存通道自检

    公开(公告)号：US20050223303A1

    公开(公告)日：2005-10-06

    申请号：US10815217

    申请日：2004-03-30

    申请人： David Zimmerman ,  Edward Weaver ,  Ramasubramanian Rajamani

    发明人： David Zimmerman ,  Edward Weaver ,  Ramasubramanian Rajamani

    IPC分类号： G11C8/00 ,  G11C29/00 ,  G11C29/08 ,  G11C29/54

    CPC分类号： G11C29/54 ,  G11C5/04 ,  G11C29/08 ,  G11C2029/5602

    摘要： A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory module, while further employing another buffer logic that is interposed between the two memory modules to pass on the test pattern, but intercept a signal received from the other memory module during the test and pass on an indication of the receipt of that signal to an analysis device to monitor the test.

    摘要翻译： 存储器模块内的缓冲器逻辑具有通过点到点总线对其进行耦合的另一个存储器模块的测试的能力，该测试模块通过自主地存储和传输跨越该点对点总线的测试模式到 其它存储器模块，同时进一步采用插入在两个存储器模块之间的另一个缓冲器逻辑来传递测试图案，但是在测试期间拦截从另一个存储器模块接收的信号，并将该信号的接收指示传递给 用于监测测试的分析设备。

    GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE
    5.
    发明申请
    GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE 有权
    用于存储器电路测试引擎的通用地址清除器

    公开(公告)号：US20140237307A1

    公开(公告)日：2014-08-21

    申请号：US13997641

    申请日：2011-12-28

    申请人： Darshan Kobla ,  David Zimmerman ,  Vimal Natarajan

    发明人： Darshan Kobla ,  David Zimmerman ,  Vimal Natarajan

    IPC分类号： G11C29/12

    CPC分类号： G11C29/12 ,  G06F12/1408 ,  G11C29/18 ,  G11C2029/1806

    摘要： A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold pro-gramming values for the generic programmable address scrambler.

    摘要翻译： 用于存储器电路测试引擎的通用地址扰乱器。 存储器件的实施例包括具有一个或多个耦合的存储器元件的存储器堆叠，内置的自测电路，其包括用于将逻辑地址映射到存储器元件的物理地址的通用可编程地址加扰器，以及一个或 更多的寄存器用于保存通用可编程地址扰频器的编程值。

    GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE
    6.
    发明申请
    GENERIC ADDRESS SCRAMBLER FOR MEMORY CIRCUIT TEST ENGINE 有权
    用于存储器电路测试引擎的通用地址清除器

    公开(公告)号：US20140013169A1

    公开(公告)日：2014-01-09

    申请号：US13997156

    申请日：2012-03-30

    申请人： Darshan Kobla ,  David Zimmerman ,  John C. Johnson ,  Vimal K. Natarajan

    发明人： Darshan Kobla ,  David Zimmerman ,  John C. Johnson ,  Vimal K. Natarajan

    IPC分类号： G11C29/18

    CPC分类号： G11C29/18 ,  G11C11/40 ,  G11C29/36

    摘要： A generic data scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory; a memory controller for the memory; a built-in self-test (BIST) circuit for the testing of the memory; and a generic data scrambler for scrambling of data according to a scrambling algorithm for the memory, where each algorithm is based on values of an address for data. The generic data scrambler includes a programmable lookup table to hold values for each possible outcome of the algorithm, the lookup table to generate a set of data factors, and a logic for combining the data with the data factors to generate scrambled data.

    摘要翻译： 用于存储器电路测试引擎的通用数据扰频器。 存储器件的实施例包括存储器; 用于存储器的存储器控​​制器; 内置自检（BIST）电路，用于测试存储器; 以及根据用于存储器的加扰算法对数据进行加扰的通用数据加扰器，其中每个算法基于用于数据的地址的值。 通用数据加扰器包括可编程查找表，用于保存算法的每个可能结果的值，用于生成一组数据因子的查找表，以及用于将数据与数据因子组合以产生加扰数据的逻辑。

    Bead applicator
    7.
    发明授权
    Bead applicator 有权
    珠涂抹器

    公开(公告)号：US08061295B2

    公开(公告)日：2011-11-22

    申请号：US12259293

    申请日：2008-10-27

    申请人： David Zimmerman ,  Russell Francis ,  Michael Orlando ,  Ryan Vodicka

    发明人： David Zimmerman ,  Russell Francis ,  Michael Orlando ,  Ryan Vodicka

    IPC分类号： B05C19/00 ,  B05B3/00 ,  B65G53/50

    CPC分类号： E01C23/166 ,  B05B7/1413 ,  B05B7/1422

    摘要： A bead applicator for embedding particulates in wet paint, includes a blower directing air into an attached series of connected pipes; a particulate hopper, and a tubular particulate supply line connecting an outlet opening from the hopper to a venturi inlet opening at a low pressure point of a venturi tube. The series of connected pipes includes, in order, the venturi tube, a rigid tubular wand, and a dispensing nozzle. The wand, an inlet of the nozzle, and an outlet of the nozzle all have approximately the same, or greater, inside cross-sectional area relative to that of an outlet of the venturi tube; and the nozzle fans out to a long and narrow shaped outlet. Preferably a flexible hose is included in the series of connected pipes; the hose having approximately the same, or greater, inside cross-sectional area relative to that of the venturi tube outlet, and the nozzle outlet is bent over.

    摘要翻译： 用于将微粒包埋在湿涂料中的珠子涂布器包括将空气引导到连接的一系列连接的管道中的鼓风机; 颗粒料斗和管状颗粒供应管线，其将来自料斗的出口开口连接到文丘里管的低压点处的文丘里管入口。 所连接的管道系列依次包括文氏管，刚性管状棒和分配喷嘴。 喷嘴的入口和喷嘴的出口全部具有与文氏管的出口大致相同或更大的内部横截面积; 并且喷嘴风扇出口到长而窄的形状的出口。 优选地，一系列连接的管中包括柔性软管; 软管具有与文丘里管出口大致相同或更大的内部横截面积，并且喷嘴出口弯曲。

    BEAD APPLICATOR
    8.
    发明申请
    BEAD APPLICATOR 有权
    珠子应用

    公开(公告)号：US20090110813A1

    公开(公告)日：2009-04-30

    申请号：US12259293

    申请日：2008-10-27

    申请人： David Zimmerman ,  Russell Francis ,  Michael Orlando ,  Ryan Vodicka

    发明人： David Zimmerman ,  Russell Francis ,  Michael Orlando ,  Ryan Vodicka

    IPC分类号： E01C17/00

    CPC分类号： E01C23/166 ,  B05B7/1413 ,  B05B7/1422

    摘要： A bead applicator for embedding particulates in wet paint, includes a blower directing air into an attached series of connected pipes; a particulate hopper, and a tubular particulate supply line connecting an outlet opening from the hopper to a venturi inlet opening at a low pressure point of a venturi tube. The series of connected pipes includes, in order, the venturi tube, a rigid tubular wand, and a dispensing nozzle. The wand, an inlet of the nozzle, and an outlet of the nozzle all have approximately the same, or greater, inside cross-sectional area relative to that of an outlet of the venturi tube; and the nozzle fans out to a long and narrow shaped outlet. Preferably a flexible hose is included in the series of connected pipes; the hose having approximately the same, or greater, inside cross-sectional area relative to that of the venturi tube outlet, and the nozzle outlet is bent over.

    摘要翻译： 用于将微粒包埋在湿涂料中的珠子涂布器包括将空气引导到连接的一系列连接的管道中的鼓风机; 颗粒料斗和管状颗粒供应管线，其将来自料斗的出口开口连接到文丘里管的低压点处的文丘里管入口。 所连接的管道系列依次包括文氏管，刚性管状棒和分配喷嘴。 喷嘴的入口和喷嘴的出口全部具有与文氏管的出口大致相同或更大的内部横截面积; 并且喷嘴风扇出口到长而窄的形状的出口。 优选地，一系列连接的管中包括柔性软管; 软管具有与文丘里管出口大致相同或更大的内部横截面积，并且喷嘴出口弯曲。