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公开(公告)号：US5003459A
公开(公告)日：1991-03-26
申请号：US176595
申请日：1988-04-01
IPC分类号： G06F12/10
CPC分类号： G06F12/1045
摘要： The invention is directed to a cache memory system in a data processor including a virtual cache memory, a physical cache memory, a virtual to physical translation buffer, a physical to virtual backmap, an Old-PA pointer and a lockout register. The backmap implements invalidates by clearing the valid flags in virtual cache memory. The Old-PA pointer indicates the backmap entry to be invalidated after a reference misses in the virtual cache. The physical address for data written to virtual cache memory is entered to Old-PA pointer by the translation buffer. The lockout register arrests all references to data which may have synonyms in virtual cache memory. The backmap is also used to invalidate any synonyms.
摘要翻译： 本发明涉及包括虚拟高速缓冲存储器，物理高速缓冲存储器，虚拟到物理转换缓冲器，物理到虚拟背景图，旧PA指针和锁定寄存器的数据处理器中的高速缓冲存储器系统。 反向映射通过清除虚拟高速缓存中的有效标志来实现无效。 Old-PA指针指示在虚拟缓存中的引用未命中之后，将无效的背景条目。 写入虚拟高速缓冲存储器的数据的物理地址由转换缓冲区输入到旧PA指针。 锁定寄存器阻止对虚拟高速缓冲存储器中可能具有同义词的数据的所有引用。 背景图也用于使任何同义词无效。
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2.发明授权System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command 失效仅当指令高速缓存地址和数据高速缓存地址匹配并执行从异常或中断返回命令执行时，仅用于刷新指令缓存的系统
公开(公告)号：US5214770A
公开(公告)日：1993-05-25
申请号：US541485
申请日：1990-06-21
IPC分类号： G06F9/38
CPC分类号： G06F9/3812 , G06F9/3861
摘要： A method and apparatus for optimizing the performance of a multiple cache system computer having separate caches for data and instructions in which all writes to the data cache are monitored. If the address tag of the item being written matches one of a list of tags representing valid instructions currently stored in the instruction cache, a flag called I.sub.-- FLUSH.sub.-- ON.sub.-- REI is set. Until this flag is set, REI (Return from Exception or Interrupt) instructions will not flush the instruction cache. When the flag is set, an REI command will also flush or clear the instruction cache. Thus, the instruction cache is only flushed when an address referenced by an instruction is modified, so as to reduce the number of times the cache is flushed and optimize the computer's speed of operation.
摘要翻译： 一种用于优化具有用于数据和指令的单独高速缓存的多高速缓存系统计算机的性能的方法和装置，其中监视对数据高速缓存的所有写入。 如果正在写入的项目的地址标签与表示当前存储在指令高速缓冲存储器中的有效指令的标签列表中的一个匹配，则设置称为I-FLUSH-ON-REI的标志。 在设置此标志之前，REI（从异常或中断返回）指令不会刷新指令高速缓存。 当标志置位时，REI命令也将刷新或清除指令高速缓存。 因此，当指令引用的地址被修改时，指令高速缓存仅被刷新，以便减少高速缓存刷新的次数并优化计算机的操作速度。
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公开(公告)号：US5038278A
公开(公告)日：1991-08-06
申请号：US611337
申请日：1990-11-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0842
摘要： During the operation of a computer system whose processor is supported by virtual cache memory, the cache must be cleared and refilled to allow the replacement of old data with more current data. The cache is filled with either P or N (N>P) blocks of data. Numerous methods for dynamically selecting N or P blocks of data are possible. For instance, immediately after the cache has been flushed, the miss is refilled with N blocks, moving data to the cache at high speed. Once the cache is mostly full, the miss tends to be refilled with P blocks. This maintains the currency of the data in the cache, while simultaneously avoiding writing-over of data already in the cache. The invention is useful in a multi-user/multi-tasking system where the program being run changes frequently, necessitating flushing and clearing the cache frequently.
摘要翻译： 在处理器由虚拟高速缓冲存储器支持的计算机系统的操作期间，必须清除缓存并重新填充以允许用更多当前数据替换旧数据。 高速缓存用P或N（N> P）数据块填充。 用于动态选择N或P个数据块的许多方法是可能的。 例如，在高速缓冲存储器被刷新之后，错误将被重新填充N个块，将数据高速移动到高速缓存。 一旦缓存大部分已满，则错误将被重新填充P块。 这将保持高速缓存中的数据的货币，同时避免缓存中已经存在的数据的写入。 本发明在运行程序频繁变化的多用户/多任务系统中是有用的，需要频繁地刷新和清除缓存。
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公开(公告)号：US5828874A
公开(公告)日：1998-10-27
申请号：US626868
申请日：1996-06-05
CPC分类号： G06F9/3806 , G06F9/30043 , G06F9/3012 , G06F9/30134 , G06F9/30141 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A branch prediction apparatus includes a predicted past history device, and a a branch prediction device. The predicted past history device is operable to receive an indication of a branch instruction and to output a pattern of past predictions of branch directions for the indicated branch instruction. The pattern of past predictions includes at least one prediction of a branch direction for which the correctness of the prediction has not been determined The branch prediction device is operable to receive the pattern of past predictions of branch directions for the indicated branch instruction and to output a predicted branch direction for the indicated branch instruction based on the received pattern of past predictions.
摘要翻译： 分支预测装置包括预测的过去历史装置和分支预测装置。 预测的过去历史装置可操作以接收分支指令的指示并输出针对所指示的分支指令的分支方向的过去预测的模式。 过去预测的模式包括尚未确定预测的正确性的分支方向的至少一个预测。分支预测装置可操作以接收针对所指示的分支指令的分支方向的过去预测的模式，并输出 基于接收到的过去预测模式，为指示的分支指令预测分支方向。
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公开(公告)号：US5581719A
公开(公告)日：1996-12-03
申请号：US401656
申请日：1995-03-10
CPC分类号： G06F9/3863 , G06F9/30054 , G06F9/3012 , G06F9/30141 , G06F9/3806 , G06F9/3814 , G06F9/3848
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译： 流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由所述指令组馈送的指令调度器，以从所述指令处理器重新排序所述指令集的发布。 映射的寄存器操作数字段在指令发布之前与所述重新排序的指令集的相应指令相关联。 处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。 处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。
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公开(公告)号：US5283873A
公开(公告)日：1994-02-01
申请号：US546364
申请日：1990-06-29
CPC分类号： G06F9/3806
摘要： A next line prediction mechanism for predicting a next instruction index to an instruction cache of a computer pipeline, has a latency equal to the cycle time of the instruction cache to maximize the instruction bandwidth out of the instruction cache. The instruction cache outputs a block of instructions with each fetch initiated by a next instruction index provided by the line prediction mechanism. The instructions of the block are processed in parallel for instruction decode and branch prediction to maintain a high rate of instruction flow through the pipeline.
摘要翻译： 用于预测对计算机流水线的指令高速缓存的下一个指令索引的下一行预测机制具有等于指令高速缓冲存储器的循环时间的等待时间，以使指令高速缓存中的指令带宽最大化。 指令高速缓存输出由行预测机制提供的下一指令索引发起的每次提取的指令块。 块的指令被并行处理，用于指令解码和分支预测，以保持高流量的指令流经管线。
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7.发明授权Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery 失效具有包含顺序列表的寄存器映射系统的寄存器映射系统，用于在精确的分支后恢复中预测循环中的寄存器
公开(公告)号：US5197132A
公开(公告)日：1993-03-23
申请号：US546411
申请日：1990-06-29
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3863
摘要： A register map having a free list of available physical locations in a register file, a log containing a sequential listing of logical registers changed during a predetermined number of cycles, a back-up map associating the logical registers with corresponding physical homes at a back-up point in a computer pipeline operation and a predicted map associating the logical registers with corresponding physical homes at a current point in the computer pipeline operation. A set of valid bits is associated with the maps to indicate whether a particular logical register is to be taken from the back-up map or the predicted map indication of a corresponding physical home. The valid bits can be "flash cleared" in a single cycle to back-up the computer pipeline to the back-up point during a trap event.
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8.发明授权Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline 失效使用环形缓冲器的SUBROUTINE返回预测机制，并与实际地址进行比较以预测地址以验证或冲洗管道
公开(公告)号：US5179673A
公开(公告)日：1993-01-12
申请号：US451943
申请日：1989-12-18
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/4426
摘要： A method and arrangement for producing a predicted subroutine return address in response to entry of a subroutine return instruction in a computer pipeline that has a ring pointer counter and a ring buffer coupled to the ring pointer counter. The ring pointer counter contains a ring pointer that is changed when either a subroutine call instruction or return instruction enters the computer pipeline. The ring buffer has buffer locations which store a value present at its input into the buffer location pointed to by the ring pointer when a subroutine call instruction enters the pipeline. The ring buffer provides a value from the buffer location pointed to by the ring pointer when a subroutine return instruction enters the computer pipeline, this provided value being the predicted subroutine return address.
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公开(公告)号：US5619662A
公开(公告)日：1997-04-08
申请号：US289613
申请日：1994-08-12
CPC分类号： G06F9/3863 , G06F9/3012 , G06F9/30141 , G06F9/322 , G06F9/3802 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译： 流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从指令处理器重新排序指令集的发布。 映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。 处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。 处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。
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公开(公告)号：US5564118A
公开(公告)日：1996-10-08
申请号：US352291
申请日：1994-12-08
CPC分类号： G06F9/3806 , G06F9/30043 , G06F9/3012 , G06F9/30134 , G06F9/30141 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译： 流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由所述指令组馈送的指令调度器，以从所述指令处理器重新排序所述指令集的发布。 映射的寄存器操作数字段在指令发布之前与所述重新排序的指令集的相应指令相关联。 处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。 处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。
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