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公开(公告)号：US09071325B2
公开(公告)日：2015-06-30
申请号：US13232873
申请日：2011-09-14
CPC分类号： H04B1/1638 , H04B1/006 , H04B1/1018
摘要： A low noise receiver includes a downconverter configured to receive a radio frequency (RF) signal, the downconverter comprising a switching architecture configured to generate a plurality of output phases based on a respective plurality of local oscillator (LO) signals, a differencing circuit configured to combine the plurality of output phases such that an nth output phase is differenced with an (n+K)th output phase, resulting in gain-added output phases, and a summation filter configured to receive the gain-added output phases and configured to combine the gain-added output phases such that a response of the receiver effectively reduces odd harmonics of the RF signal.
摘要翻译： 低噪声接收器包括被配置为接收射频（RF）信号的下变频器，所述下变频器包括被配置为基于相应的多个本地振荡器（LO）信号产生多个输出相位的开关结构;差分电路，被配置为 组合多个输出相位，使得第n个输出相位与第（n + K）个输出相位差，产生增益输出相位，以及相加滤波器，被配置为接收增益输出相位并被配置为组合 增益输出相位使得接收器的响应有效地降低了RF信号的奇次谐波。
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公开(公告)号：US20120063555A1
公开(公告)日：2012-03-15
申请号：US13232873
申请日：2011-09-14
IPC分类号： H04B1/10
CPC分类号： H04B1/1638 , H04B1/006 , H04B1/1018
摘要： A low noise receiver includes a downconverter configured to receive a radio frequency (RF) signal, the downconverter comprising a switching architecture configured to generate a plurality of output phases based on a respective plurality of local oscillator (LO) signals, a differencing circuit configured to combine the plurality of output phases such that an nth output phase is differenced with an (n+K)th output phase, resulting in gain-added output phases, and a summation filter configured to receive the gain-added output phases and configured to combine the gain-added output phases such that a response of the receiver effectively reduces odd harmonics of the RF signal.
摘要翻译： 低噪声接收器包括被配置为接收射频（RF）信号的下变频器，所述下变频器包括被配置为基于相应的多个本地振荡器（LO）信号产生多个输出相位的开关结构;差分电路，被配置为 组合多个输出相位，使得第n个输出相位与第（n + K）个输出相位差，产生增益输出相位，以及相加滤波器，被配置为接收增益输出相位并被配置为组合 增益输出相位使得接收器的响应有效地降低了RF信号的奇次谐波。
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公开(公告)号：US08406707B2
公开(公告)日：2013-03-26
申请号：US13419741
申请日：2012-03-14
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译： 提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。 一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。 一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。 本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。 三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。 谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。
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公开(公告)号：US20120171973A1
公开(公告)日：2012-07-05
申请号：US13419741
申请日：2012-03-14
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译： 提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。 一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。 一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。 本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。 三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。 谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。
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公开(公告)号：US20090325510A1
公开(公告)日：2009-12-31
申请号：US12145599
申请日：2008-06-25
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译： 提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。 一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。 一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。 本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。 三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。 谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。
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6.发明申请System And Method For Low Noise Output Divider And Buffer Having Low Current Consumption 有权低噪声输出分频器和低电流消耗的缓冲器系统和方法公开(公告)号：US20090042517A1
公开(公告)日：2009-02-12
申请号：US11837003
申请日：2007-08-10
摘要： A low noise divider includes a voltage controlled oscillator (VCO) having a first frequency output, a frequency divider configured to receive the first frequency output and configured to provide a second frequency output; and a buffer circuit configured to receive the first frequency output and the second frequency output, the buffer circuit configured to provide the second frequency output as an output of the low noise divider, where a phase noise of the second frequency output is dependent only on a phase noise of the first frequency output.
摘要翻译： 低噪声分压器包括具有第一频率输出的压控振荡器（VCO），配置成接收第一频率输出并被配置为提供第二频率输出的分频器; 以及缓冲电路，被配置为接收所述第一频率输出和所述第二频率输出，所述缓冲电路被配置为提供所述第二频率输出作为所述低噪声分频器的输出，其中所述第二频率输出的相位噪声仅依赖于 第一频率输出的相位噪声。
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7.发明申请公开(公告)号：US20090036069A1
公开(公告)日：2009-02-05
申请号：US12144878
申请日：2008-06-24
申请人： Utku Seckin , Rajasekhar Pullela , Bipul Agarwal
发明人： Utku Seckin , Rajasekhar Pullela , Bipul Agarwal
IPC分类号： H04B1/04
CPC分类号： H03D7/1425 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/16 , H03D7/165 , H03D7/18 , H03D2200/0019 , H04B1/28 , H04B2001/0491
摘要： An upconverter includes a switching architecture configured to receive an input signal, a first local oscillator (LO) signal, and a second local oscillator (2LO) signal that is at a frequency that is twice a frequency of the local oscillator (LO) signal, wherein the switching architecture is configured to switch the input signal on transitions of the second local oscillator (2LO) signal, and wherein the first local oscillator signal and the second local oscillator signal are combined to form combined LO 2LO switching signals.
摘要翻译： 上变频器包括被配置为接收输入信号的开关结构，第一本地振荡器（LO）信号和处于本地振荡器（LO）信号的频率的两倍的频率的第二本地振荡器（2LO）信号， 其中所述交换架构被配置为在所述第二本地振荡器（2LO）信号的转换上切换所述输入信号，并且其中所述第一本地振荡器信号和所述第二本地振荡器信号被组合以形成组合的LO 2LO切换信号。
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公开(公告)号：US08165538B2
公开(公告)日：2012-04-24
申请号：US12145599
申请日：2008-06-25
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译： 提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。 一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。 一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。 本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。 三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。 谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。
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9.发明授权Single chip GSM/EDGE transceiver architecture with closed loop power control 失效单芯片GSM / EDGE收发器架构，具有闭环功率控制公开(公告)号：US07483678B2
公开(公告)日：2009-01-27
申请号：US11235907
申请日：2005-09-27
IPC分类号： H04B1/38
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.
摘要翻译： 单芯片GSM / EDGE收发器包括全差分接收链，接收链中的次谐波混频器，次谐波混频器被配置为接收射频（RF）输入信号和本地振荡器（LO）信号，该信号被相移 一个标称45度的合成器，以及具有压控振荡器并具有至少一个分频器以产生所需发射和接收LO信号的合成器。 收发器还包括具有闭合功率控制回路和谐波抑制调制器的发射机，其使用通过设计成允许合成器在没有倍频器的情况下开发发射和接收LO信号的频率计划成为可能。
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10.发明申请Single chip GSM/EDGE transceiver architecture with closed loop power control 失效单芯片GSM / EDGE收发器架构，具有闭环功率控制公开(公告)号：US20070072577A1
公开(公告)日：2007-03-29
申请号：US11235907
申请日：2005-09-27
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.
摘要翻译： 单芯片GSM / EDGE收发器包括全差分接收链，接收链中的次谐波混频器，次谐波混频器被配置为接收射频（RF）输入信号和本地振荡器（LO）信号，该信号被相移 一个标称45度的合成器，以及具有压控振荡器并具有至少一个分频器以产生所需发射和接收LO信号的合成器。 收发器还包括具有闭合功率控制回路和谐波抑制调制器的发射机，其使用通过设计成允许合成器在没有倍频器的情况下开发发射和接收LO信号的频率计划成为可能。
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