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1.发明申请Power electronic package having two substrates with multiple semiconductor chips and electronic components 有权具有两个具有多个半导体芯片和电子部件的基板的电力电子封装公开(公告)号：US20080054439A1
公开(公告)日：2008-03-06
申请号：US11511516
申请日：2006-08-29
IPC分类号： H01L23/48
CPC分类号： H01L23/49844 , H01L23/5385 , H01L24/31 , H01L24/83 , H01L25/072 , H01L25/18 , H01L2224/33 , H01L2224/81894 , H01L2224/83801 , H01L2224/83894 , H01L2924/01079 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
摘要翻译： 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。
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2.发明授权Power electronic package having two substrates with multiple semiconductor chips and electronic components 有权具有两个具有多个半导体芯片和电子部件的基板的电力电子封装公开(公告)号：US08432030B2
公开(公告)日：2013-04-30
申请号：US13171788
申请日：2011-06-29
IPC分类号： H01L23/48
CPC分类号： H01L23/49844 , H01L23/5385 , H01L24/31 , H01L24/83 , H01L25/072 , H01L25/18 , H01L2224/33 , H01L2224/81894 , H01L2224/83801 , H01L2224/83894 , H01L2924/01079 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
摘要翻译： 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。
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3.发明授权Power electronic package having two substrates with multiple semiconductor chips and electronic components 有权具有两个具有多个半导体芯片和电子部件的基板的电力电子封装公开(公告)号：US07999369B2
公开(公告)日：2011-08-16
申请号：US11511516
申请日：2006-08-29
IPC分类号： H01L23/48
CPC分类号： H01L23/49844 , H01L23/5385 , H01L24/31 , H01L24/83 , H01L25/072 , H01L25/18 , H01L2224/33 , H01L2224/81894 , H01L2224/83801 , H01L2224/83894 , H01L2924/01079 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
摘要翻译： 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。
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4.发明授权Power electronic package having two substrates with multiple electronic components 有权具有两个具有多个电子部件的基板的电力电子封装公开(公告)号：US07557434B2
公开(公告)日：2009-07-07
申请号：US11511517
申请日：2006-08-29
IPC分类号： H01L23/02
CPC分类号： H01L24/72 , H01L24/01 , H01L24/33 , H01L25/072 , H01L25/18 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/15747 , H01L2924/15787 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.
摘要翻译： 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及安装在每个基板上的多个电子部件。 基板在多个接合区域彼此耦合，使得基板之间的机械分离由接合区域的数量，接合区域的布置，每个接合区域的形状和接合区域的材料 。 机械分离在电子部件中提供净轴向定向的压缩力。
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5.发明申请Power electronic package having two substrates with multiple electronic components 有权具有两个具有多个电子部件的基板的电力电子封装公开(公告)号：US20080054425A1
公开(公告)日：2008-03-06
申请号：US11511517
申请日：2006-08-29
IPC分类号： H01L23/02
CPC分类号： H01L24/72 , H01L24/01 , H01L24/33 , H01L25/072 , H01L25/18 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/15747 , H01L2924/15787 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.
摘要翻译： 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及安装在每个基板上的多个电子部件。 基板在多个接合区域彼此耦合，使得基板之间的机械分离由接合区域的数量，接合区域的布置，每个接合区域的形状以及接合区域的材料 。 机械分离在电子部件中提供净轴向定向的压缩力。
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6.发明授权公开(公告)号：US08274086B2
公开(公告)日：2012-09-25
申请号：US12458968
申请日：2009-07-28
IPC分类号： H01L29/15 , H01L31/0256
CPC分类号： H01L29/8083 , H01L29/063 , H01L29/0692 , H01L29/6609 , H01L29/66325 , H01L29/8611 , H01L29/872
摘要： A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.
摘要翻译： 宽带隙半导体器件具有晶体管单元区域，二极管形成区域，位于晶体管单元区域和二极管形成区域之间的电场弛豫区域以及围绕晶体管单元区域和二极管形成区域的外围区域。 在晶体管单元区域中，设置结型场效应晶体管。 在二极管形成区域中，设置二极管。 在电场弛豫区域中，设置隔离部。 隔离部分包括分隔晶体管单元区域和二极管形成区域的沟槽，设置在沟槽的内壁上的第一导电类型层和设置在第一导电类型层的表面上的第二导电类型层 以填补沟槽。 第一导电型层和第二导电型层提供PN结。
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7.发明申请公开(公告)号：US20100025693A1
公开(公告)日：2010-02-04
申请号：US12458968
申请日：2009-07-28
IPC分类号： H01L29/772 , H01L29/02
CPC分类号： H01L29/8083 , H01L29/063 , H01L29/0692 , H01L29/6609 , H01L29/66325 , H01L29/8611 , H01L29/872
摘要： A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.
摘要翻译： 宽带隙半导体器件具有晶体管单元区域，二极管形成区域，位于晶体管单元区域和二极管形成区域之间的电场弛豫区域以及围绕晶体管单元区域和二极管形成区域的外围区域。 在晶体管单元区域中，设置结型场效应晶体管。 在二极管形成区域中，设置二极管。 在电场弛豫区域中，设置隔离部。 隔离部分包括分隔晶体管单元区域和二极管形成区域的沟槽，设置在沟槽的内壁上的第一导电类型层和设置在第一导电类型层的表面上的第二导电类型层 以填补沟槽。 第一导电型层和第二导电型层提供PN结。
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