公开(公告)号：US20070279120A1

公开(公告)日：2007-12-06

申请号：US10583538

申请日：2004-12-03

申请人： Ralf Brederlow ,  Jeongwook Koh ,  Christian Pacha ,  Roland Thewes

发明人： Ralf Brederlow ,  Jeongwook Koh ,  Christian Pacha ,  Roland Thewes

IPC分类号： H03K17/16

CPC分类号： H03K17/162 ,  H01L2924/0002 ,  H01L2924/00

摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.

摘要翻译： 具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。 时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号 比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。 第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。 第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

公开(公告)号：US07733157B2

公开(公告)日：2010-06-08

申请号：US10583538

申请日：2004-12-03

申请人： Ralf Brederlow ,  Jeongwook Koh ,  Christian Pacha ,  Roland Thewes

发明人： Ralf Brederlow ,  Jeongwook Koh ,  Christian Pacha ,  Roland Thewes

IPC分类号： H03K17/687

CPC分类号： H03K17/162 ,  H01L2924/0002 ,  H01L2924/00

摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.

摘要翻译： 具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。 时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号 比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。 第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。 第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

公开(公告)号：US07733156B2

公开(公告)日：2010-06-08

申请号：US10570924

申请日：2004-09-01

申请人： Ralf Brederlow ,  Jeongwook Koh ,  Roland Thewes

发明人： Ralf Brederlow ,  Jeongwook Koh ,  Roland Thewes

IPC分类号： H03K17/16 ,  H03K17/687

CPC分类号： H03F3/211 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/72 ,  H03F2203/21178 ,  H03F2203/7215 ,  H01L2924/00

摘要： The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

摘要翻译： 晶体管装置包括第一和第二场效应晶体管，其包括第一和第二源极漏极连接以及用于施加第一或第二信号的控制连接。 两个场效应晶体管具有相同的导电类型。 晶体管布置被配置为使得第一信号可以以交替方式施加到第一场效应晶体管的控制连接，并且第二信号可以以与第二场效应的控制连接同时的方式施加 晶体管和/或第二信号可以被施加到第一场效应晶体管的控制连接，并且第一信号可以同时施加到第二场效应晶体管的控制连接。

公开(公告)号：US20070176634A1

公开(公告)日：2007-08-02

申请号：US10570924

申请日：2004-09-01

申请人： Ralf Brederlow ,  Jeongwook Koh ,  Roland Thewes

发明人： Ralf Brederlow ,  Jeongwook Koh ,  Roland Thewes

IPC分类号： H03K19/094

CPC分类号： H03F3/211 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/72 ,  H03F2203/21178 ,  H03F2203/7215 ,  H01L2924/00

摘要： The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

摘要翻译： 晶体管装置包括第一和第二场效应晶体管，其包括第一和第二源极漏极连接以及用于施加第一或第二信号的控制连接。 两个场效应晶体管具有相同的导电类型。 晶体管布置被配置为使得第一信号可以以交替方式施加到第一场效应晶体管的控制连接，并且第二信号可以以与第二场效应的控制连接同时的方式施加 晶体管和/或第二信号可以被施加到第一场效应晶体管的控制连接，并且第一信号可以同时施加到第二场效应晶体管的控制连接。

公开(公告)号：US20080315950A1

公开(公告)日：2008-12-25

申请号：US12203260

申请日：2008-09-03

申请人： Jeongwook Koh ,  Chun-Deok Suh ,  Eun-Chul Park

发明人： Jeongwook Koh ,  Chun-Deok Suh ,  Eun-Chul Park

IPC分类号： H03F3/45 ,  H03L7/00

CPC分类号： H03F1/26 ,  H03F3/45179 ,  H03F2200/366 ,  H03F2200/372 ,  H03F2203/45342 ,  H03F2203/45371 ,  H03F2203/45396

摘要： Integrated circuit devices include a pair of field effect transistors having shared source terminals, shared drain terminals and shared gate terminals, which may be treated herein as being electrically coupled in parallel. A switch circuit is also provided, which is configured to drive a body terminal of a first one of the pair of field effect transistors with an alternating sequence of first and second unequal body voltages. This alternating sequence is synchronized with a first clock signal. The switch circuit is also configured to drive a body terminal of a second one of the pair of field effect transistors with an alternating sequence of third and fourth unequal body voltages, which is synchronized with a second clock signal. The first and third body voltages may have equivalent magnitudes and the second and fourth body voltages may have equivalent magnitudes. The first and second clock signals may have 50% duty cycles and may be 180 degrees out-of-phase relative to each other.

摘要翻译： 集成电路器件包括具有共享源极端子，共用漏极端子和共享栅极端子的一对场效应晶体管，其可以在本文中被并入电耦合。 还提供了一种开关电路，其被配置为用第一和第二不相等体电压的交替序列来驱动一对场效应晶体管中的第一个场效应晶体管的主体端子。 该交替序列与第一时钟信号同步。 开关电路还被配置为以与第二时钟信号同步的第三和第四不等体电压的交替序列来驱动一对场效应晶体管中的第二个场效应晶体管的主体端子。 第一和第三体电压可以具有相等的量级，第二和第四体电压可以具有相等的量级。 第一和第二时钟信号可以具有50％的占空比，并且可以相对于彼此是180度异相。

公开(公告)号：US20070096820A1

公开(公告)日：2007-05-03

申请号：US11396546

申请日：2006-04-04

申请人： Jeongwook Koh ,  Han Lee ,  Hoon Kim

发明人： Jeongwook Koh ,  Han Lee ,  Hoon Kim

IPC分类号： H03F3/45

CPC分类号： H03F3/45183

摘要： The differential amplifier and an active load are provided. The differential amplifier includes a differential input section which is configured to generate a differential current according to a differential input signal; and an active load which is configured to generate a differential output signal according to the differential current. The active load includes first and second active load sections comprising a first negative feedback loop and a second negative feedback loop, respectively; and a common mode feedback section comprising a feedback current source which supplies a feedback current to the first active load section and the second active load section to form a common mode feedback path.

公开(公告)号：US20060181349A1

公开(公告)日：2006-08-17

申请号：US11339523

申请日：2006-01-26

申请人： Jeongwook Koh ,  Hoon-tae Kim ,  Kyoung-sik Seol ,  Gyu-hyeong Cho

发明人： Jeongwook Koh ,  Hoon-tae Kim ,  Kyoung-sik Seol ,  Gyu-hyeong Cho

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45052 ,  H03F2203/45244 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45366 ,  H03F2203/45458 ,  H03F2203/45466 ,  H03F2203/45492 ,  H03G1/0029

摘要： Provided is a complementary metal oxide semiconductor variable gain amplifier controlling a dB linear gain and a method of controlling the dB linear gain. The complimentary metal oxide semiconductor variable gain amplifier includes: first through fourth transistors differentially receiving first and second input voltages and amplifying the first and second input voltage using a predetermined gain; fifth and sixth transistors controlling a transconductance according to a control voltage to control the predetermined gain; and first and second resistors generating an output voltage having the predetermined gain according to an output current generated by the fifth and sixth transistors.

摘要翻译： 提供了控制dB线性增益的互补金属氧化物半导体可变增益放大器和控制dB线性增益的方法。 互补金属氧化物半导体可变增益放大器包括：第一至第四晶体管，差分地接收第一和第二输入电压，并使用预定增益放大第一和第二输入电压; 第五和第六晶体管根据控制电压控制跨导以控制预定的增益; 以及根据由第五和第六晶体管产生的输出电流产生具有预定增益的输出电压的第一和第二电阻器。

公开(公告)号：US20060181338A1

公开(公告)日：2006-08-17

申请号：US11354944

申请日：2006-02-16

申请人： Jeongwook Koh ,  Chun-deok Suh

发明人： Jeongwook Koh ,  Chun-deok Suh

IPC分类号： G05F1/10

CPC分类号： G05F3/262

摘要： A stacked CMOS current mirror using metal oxide semiconductor field effect transistors (MOSFETs) having different threshold voltages is disclosed. The stacked CMOS current mirror includes a first MOSFET having a source and a gate which are connected to a first input current terminal, a second MOSFET having a source connected to a drain of the first MOSFET, a gate connected to the gate of the first MOSFET, and a drain connected to ground, a third MOSFET having a drain connected to a second input current terminal and a gate connected to the source and the gate of the first MOSFET, and a fourth MOSFET having a drain connected to a source of the third MOSFET, a gate connected to the source and the gate of the first MOSFET, and a source connected to the ground.

摘要翻译： 公开了使用具有不同阈值电压的金属氧化物半导体场效应晶体管（MOSFET）的叠层CMOS电流镜。 堆叠的CMOS电流镜包括具有连接到第一输入电流端子的源极和栅极的第一MOSFET，具有连接到第一MOSFET的漏极的源极的第二MOSFET，连接到第一MOSFET的栅极的栅极 以及与地相连的漏极，具有连接到第二输入电流端子的漏极和连接到第一MOSFET的源极和栅极的栅极的第三MOSFET和具有连接到第三MOSFET源极的漏极的第四MOSFET MOSFET，连接到源极和第一MOSFET的栅极的栅极，以及连接到地的源极。

公开(公告)号：US20060173944A1

公开(公告)日：2006-08-03

申请号：US11338747

申请日：2006-01-25

申请人： Han-seung Lee ,  Jeongwook Koh ,  Jung-eun Lee ,  Hoang Duong ,  Sang-gug Lee

发明人： Han-seung Lee ,  Jeongwook Koh ,  Jung-eun Lee ,  Hoang Duong ,  Sang-gug Lee

IPC分类号： G06F1/02

CPC分类号： G06G7/26 ,  G06G7/24

摘要： An exponential function generator for generating an exponential generator to realize a linear region of about 60 dB required for the an ultra wide band system (UWB). Since the exponential function generator is implemented in a form of complementary metal oxide semiconductor fabrication (CMOS), compactness and operation control of the exponential function generator can be facilitated.

摘要翻译： 指数函数发生器，用于产生指数发生器以实现超宽带系统（UWB）所需的约60dB的线性区域。 由于指数函数发生器以互补金属氧化物半导体制造（CMOS）的形式实现，因此可以促进指数函数发生器的紧凑性和操作控制。

公开(公告)号：US07358811B2

公开(公告)日：2008-04-15

申请号：US11339523

申请日：2006-01-26

申请人： Jeongwook Koh ,  Hoon-tae Kim ,  Kyoung-sik Seol ,  Gyu-hyeong Cho

发明人： Jeongwook Koh ,  Hoon-tae Kim ,  Kyoung-sik Seol ,  Gyu-hyeong Cho

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45052 ,  H03F2203/45244 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45366 ,  H03F2203/45458 ,  H03F2203/45466 ,  H03F2203/45492 ,  H03G1/0029

摘要： Provided is a complementary metal oxide semiconductor variable gain amplifier controlling a dB linear gain and a method of controlling the dB linear gain. The complimentary metal oxide semiconductor variable gain amplifier includes: first through fourth transistors differentially receiving first and second input voltages and amplifying the first and second input voltage using a predetermined gain; fifth and sixth transistors controlling a transconductance according to a control voltage to control the predetermined gain; and first and second resistors generating an output voltage having the predetermined gain according to an output current generated by the fifth and sixth transistors.

摘要翻译： 提供了控制dB线性增益的互补金属氧化物半导体可变增益放大器和控制dB线性增益的方法。 互补金属氧化物半导体可变增益放大器包括：第一至第四晶体管，差分地接收第一和第二输入电压，并使用预定增益放大第一和第二输入电压; 第五和第六晶体管根据控制电压控制跨导以控制预定的增益; 以及根据由第五和第六晶体管产生的输出电流产生具有预定增益的输出电压的第一和第二电阻器。