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公开(公告)号：US20050220108A1
公开(公告)日：2005-10-06
申请号：US10939859
申请日：2004-09-13
申请人： Ralf Flemming , Matthias Baer , Uwe Eckhardt , Ulrich Hensel , William Kern , Stephan Rosner
发明人： Ralf Flemming , Matthias Baer , Uwe Eckhardt , Ulrich Hensel , William Kern , Stephan Rosner
摘要： A WLAN (Wireless Local Area Network) communication device and method are provided where a MAC (Medium Access Control) control unit controls access to a wireless medium. The MAC control unit is capable of selectively applying any one of at least two different control mechanisms to data to be transmitted. The data received from a target system comprises data frames, each having associated an individual control header comprising control information. The control information specifies at least one control mechanism to be applied to data of the associated data frame. The MAC control unit extracts control information from each control header associated to a data frame, and selects a control mechanism specified by the extracted control information.
摘要翻译： 提供WLAN（无线局域网）通信设备和方法，其中MAC（介质访问控制）控制单元控制对无线介质的访问。 MAC控制单元能够选择性地将至少两个不同的控制机制中的任何一个应用于要发送的数据。 从目标系统接收的数据包括数据帧，每个数据帧具有包括控制信息的单个控制报头。 控制信息指定要应用于相关联的数据帧的数据的至少一个控制机制。 MAC控制单元从与数据帧相关联的每个控制头提取控制信息，并且选择由所提取的控制信息指定的控制机制。
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公开(公告)号：US20070047538A1
公开(公告)日：2007-03-01
申请号：US11591086
申请日：2006-11-01
申请人： Stephan Rosner , William Kern , Ralf Flemming , Matthias Baer , Stephen Novak
发明人： Stephan Rosner , William Kern , Ralf Flemming , Matthias Baer , Stephen Novak
IPC分类号： H04L12/50
CPC分类号： H04L49/901 , H04L49/9057 , H04L69/12 , H04W72/12
摘要： A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40).
摘要翻译： 无线计算机系统（30）形成为具有主机部分（31）和无线硬件部分（40）。 传输帧的第一部分形成在主机部分（31）的系统存储器（36）中，并且传输帧的第二部分形成在无线硬件部分（40）中。 无线硬件部分（40）开始发送第一传输帧部分，同时将第二传输帧部分从系统存储器（36）下载到无线硬件部分（40）中。
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公开(公告)号：US07729382B2
公开(公告)日：2010-06-01
申请号：US11591086
申请日：2006-11-01
IPC分类号： H04L12/413
CPC分类号： H04L49/901 , H04L49/9057 , H04L69/12 , H04W72/12
摘要： A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40).
摘要翻译： 无线计算机系统（30）形成为具有主机部分（31）和无线硬件部分（40）。 传输帧的第一部分形成在主机部分（31）的系统存储器（36）中，并且传输帧的第二部分形成在无线硬件部分（40）中。 无线硬件部分（40）开始发送第一传输帧部分，同时将第二传输帧部分从系统存储器（36）下载到无线硬件部分（40）中。
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公开(公告)号：US07149213B1
公开(公告)日：2006-12-12
申请号：US10147426
申请日：2002-05-16
IPC分类号： H04L12/50
CPC分类号： H04L49/901 , H04L49/9057 , H04L69/12 , H04W72/12
摘要： A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40).
摘要翻译： 无线计算机系统（30）形成为具有主机部分（31）和无线硬件部分（40）。 传输帧的第一部分形成在主机部分（31）的系统存储器（36）中，并且传输帧的第二部分形成在无线硬件部分（40）中。 无线硬件部分（40）开始发送第一传输帧部分，同时将第二传输帧部分从系统存储器（36）下载到无线硬件部分（40）中。
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5.发明授权Method and apparatus for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers 失效通过使用两级DMA传输，通过PCI总线访问具有时变响应的存储器的方法和装置公开(公告)号：US07047328B1
公开(公告)日：2006-05-16
申请号：US09904748
申请日：2001-07-13
申请人： Stephan Rosner , Jörg Winkler , Ralf Flemming , Stephen T. Novak
发明人： Stephan Rosner , Jörg Winkler , Ralf Flemming , Stephen T. Novak
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F2213/0024
摘要： The invention relates to an apparatus and a method for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers. The invention provides a method for executing a read request over a PCI bus by transferring the requested data from a main memory of a PCI card to a device located on the PCI bus, comprising the steps of obtaining an access request from a read access queue, transferring, by a first DMA transfer, the requested data from the main memory to a buffer memory on the PCI card, and transferring, by a second DMA transfer, the data from the buffer memory to the device.
摘要翻译： 本发明涉及一种通过使用两级DMA传输来访问具有PCI总线的时变响应的存储器的装置和方法。 本发明提供了一种用于通过将所请求的数据从PCI卡的主存储器传送到位于PCI总线上的设备来执行PCI总线上的读取请求的方法，包括以下步骤：从读访问队列获取访问请求， 通过第一DMA传送将请求的数据从主存储器传送到PCI卡上的缓冲存储器，并且通过第二DMA传输将数据从缓冲存储器传送到设备。
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公开(公告)号：US07313104B1
公开(公告)日：2007-12-25
申请号：US10147413
申请日：2002-05-16
摘要： A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40). Bus latencies are masked by at least overlapping transmitting the first portion of the transmit frame while downloading the second portion.
摘要翻译： 无线计算机系统（30）形成为具有主机部分（31）和无线硬件部分（40）。 传输帧的第一部分形成在主机部分（31）的系统存储器（36）中，并且传输帧的第二部分形成在无线硬件部分（40）中。 无线硬件部分（40）开始发送第一传输帧部分，同时将第二传输帧部分从系统存储器（36）下载到无线硬件部分（40）中。 在下载第二部分的同时至少重叠传输发送帧的第一部分来掩蔽总线延迟。
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公开(公告)号：US08230154B2
公开(公告)日：2012-07-24
申请号：US11625150
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/06
CPC分类号： G06F9/5016 , G11C15/00 , G11C16/26
摘要： A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
摘要翻译： 提供了一种促进存储器件中的读取访问的系统。 该系统包括存储与一个或多个软件线程相关联的高阶地址的多个行地址缓冲器。 系统还包括多个行数据缓冲器。 行数据缓冲器各自与至少一个行地址缓冲器相关联，并且在行地址缓冲器的高位地址的范围内存储行数据。 该系统通过限制与上下文切换相关的延迟来增加存储器件性能。 多个行地址缓冲器和行数据缓冲器使得软件线程能够与一个或多个缓冲器相关联，并且尽管上下文切换来维持有效的后续存储器访问。
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8.发明申请MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS 有权改善阅读/写入性能并为移动系统提供低延迟的内存缓冲系统公开(公告)号：US20090132736A1
公开(公告)日：2009-05-21
申请号：US11943544
申请日：2007-11-20
申请人： Qamrul Hasan , Stephan Rosner , Roger Dwain Isaac
发明人： Qamrul Hasan , Stephan Rosner , Roger Dwain Isaac
IPC分类号： G06F13/00
CPC分类号： G06F13/161 , G06F13/1605 , G06F13/1626 , G06F13/1642 , G06F13/1673 , G06F13/1694 , G06F13/372 , G06F13/4282
摘要： A memory buffering system is disclosed that arbitrates bus ownership through all arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.
摘要翻译： 公开了一种存储器缓冲系统，其通过用于链式架构中的存储器元件的所有仲裁方案仲裁总线所有权。 统一的主机内存控制器仲裁总线所有权，将其传输到统一的内存缓冲区和链式体系结构中的其他缓冲区。 该系统在具有链路架构和并行架构中的总线的通信系统中使用。
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公开(公告)号：US20080177930A1
公开(公告)日：2008-07-24
申请号：US11625150
申请日：2007-01-19
申请人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
发明人： Roger Isaac , Stephan Rosner , Qamrul Hasan , Jeremy Mah
IPC分类号： G06F12/02
CPC分类号： G06F9/5016 , G11C15/00 , G11C16/26
摘要： A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.
摘要翻译： 提供了一种促进存储器件中的读取访问的系统。 该系统包括存储与一个或多个软件线程相关联的高阶地址的多个行地址缓冲器。 系统还包括多个行数据缓冲器。 行数据缓冲器各自与至少一个行地址缓冲器相关联，并且在行地址缓冲器的高位地址的范围内存储行数据。 该系统通过限制与上下文切换相关的延迟来增加存储器件性能。 多个行地址缓冲器和行数据缓冲器使得软件线程能够与一个或多个缓冲器相关联，并且尽管上下文切换来维持有效的后续存储器访问。
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公开(公告)号：US07239640B1
公开(公告)日：2007-07-03
申请号：US09587722
申请日：2000-06-05
申请人： Jorg Winkler , Stephan Rosner , Ralf Fleming , Stephen T. Novak
发明人： Jorg Winkler , Stephan Rosner , Ralf Fleming , Stephen T. Novak
IPC分类号： H04L12/56
CPC分类号： H04L12/56 , H04L2012/5616 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要： The invention relates to a method and an apparatus for receiving and transmitting asynchronous transfer mode (ATM) cell streams over a bus. The invention provides a method for receiving ATM cells in a host from a client over a bus, comprising the steps of determining whether an ATM cell in a first storage device within the client is ready to be transferred over the bus to a second storage device within the host, preventing overflow of the second storage device by calculating a first available cell space in the second storage device as a function of a write value, a read value image and a size value of the second storage device, and transferring an ATM cell from the first storage device to the second storage device.
摘要翻译： 本发明涉及一种通过总线接收和发送异步传输模式（ATM）信元流的方法和装置。 本发明提供了一种用于通过总线从客户端接收主机中的ATM信元的方法，包括以下步骤：确定客户端内的第一存储设备中的ATM信元是否准备好通过总线传送到第二存储设备内的第二存储设备 主机，通过根据第二存储装置的写入值，读取值图像和大小值计算第二存储装置中的第一可用单元空间来防止第二存储装置的溢出，并且将ATM信元从 第一存储设备到第二存储设备。
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