Method and apparatus for reducing jitter in a phase locked loop circuit
    1.
    发明授权
    Method and apparatus for reducing jitter in a phase locked loop circuit 失效
    减少锁相环电路抖动的方法和装置

    公开(公告)号:US5491439A

    公开(公告)日:1996-02-13

    申请号:US298695

    申请日:1994-08-31

    摘要: A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.

    摘要翻译: 锁相环电路包括相位/频率检测器,该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。 一对电荷泵接收INC和DEC脉冲。 一个电荷泵是差分泵,并具有电压控制的共模反馈电路,以保持共模控制电压。 通过该电荷泵将差分电流输出到环路滤波电容器。 另一个电荷泵是一个单端输出泵,它向电流控制振荡器提供电流,该电流控制振荡器也接收电压到电流转换器的输入。 电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。 提供了一种抖动控制电路,可减少锁定相中当前受控振荡器输出的抖动。 而且,提供了与时间无关的锁定指示器,并且当环路进入锁定状态时提供锁定指示。