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260 条记录 (耗时 0.033 秒)

    Low input impedance line/bus receiver
    2.
    发明授权
    Low input impedance line/bus receiver 失效
    低输入阻抗线路/总线接收器

    公开(公告)号：US06498518B1

    公开(公告)日：2002-12-24

    申请号：US09617680

    申请日：2000-07-14

    申请人： Russell J. Houghton ,  Jack A. Mandelman ,  Azzouz Nezar ,  Wilbur D. Pricer ,  William R. Tonti

    发明人： Russell J. Houghton ,  Jack A. Mandelman ,  Azzouz Nezar ,  Wilbur D. Pricer ,  William R. Tonti

    IPC分类号： H03K522

    CPC分类号： H04L25/0292 ,  H03K5/24 ,  H03K19/017554

    摘要： A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.

    摘要翻译： 连接到电源端子并且具有至少一个输入端子和至少一个输出端子的电流感测电路包括至少一个具有基极，发射极和集电极的双极晶体管，连接到电源端子的至少一个电流镜放大器， 所述电流镜放大器具有连接到所述集电极并且具有连接到所述发射极的至少一个输出的输入端和连接到所述基极的DC电压源。

    Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion
    3.
    发明授权
    Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion 失效
    用于使用受控栅极耗尽的CMOS器件形成混合高压（HV / LV）晶体管的方法

    公开(公告)号：US06436749B1

    公开(公告)日：2002-08-20

    申请号：US09658655

    申请日：2000-09-08

    申请人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

    发明人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

    IPC分类号： H01L218238

    CPC分类号： H01L27/092 ,  H01L21/823842

    摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.

    摘要翻译： 公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。 在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。 阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。 因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。

    Structures and methods of anti-fuse formation in SOI
    4.
    发明授权
    Structures and methods of anti-fuse formation in SOI 失效
    SOI中抗熔丝形成的结构和方法

    公开(公告)号：US06972220B2

    公开(公告)日：2005-12-06

    申请号：US10366298

    申请日：2003-02-12

    申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12 ,  H01L21/00

    CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

    摘要翻译： 可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的反熔丝结构形成在复合衬底上，例如绝缘体上硅 通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。 反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。 绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。 由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。 因此实现了自动修复而不中断操作的可能性。

    Method of forming connection and anti-fuse in layered substrate such as SOI
    5.
    发明授权
    Method of forming connection and anti-fuse in layered substrate such as SOI 有权
    在诸如SOI的层状衬底中形成连接和反熔丝的方法

    公开(公告)号：US07226816B2

    公开(公告)日：2007-06-05

    申请号：US11055106

    申请日：2005-02-11

    申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

    摘要翻译： 可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的抗熔丝结构形成在复合衬底上，例如绝缘体上硅 通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。 反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。 绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。 由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。 因此实现了自动修复而不中断操作的可能性。

    Method for novel SOI DRAM BICMOS NPN
    6.
    发明授权
    Method for novel SOI DRAM BICMOS NPN 失效
    新型SOI DRAM BICMOS NPN的方法

    公开(公告)号：US06492211B1

    公开(公告)日：2002-12-10

    申请号：US09656819

    申请日：2000-09-07

    申请人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

    发明人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

    IPC分类号： H01L2100

    CPC分类号： H01L27/10894 ,  G11C7/065 ,  G11C2207/005 ,  G11C2207/065 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/10897 ,  H01L27/1203

    摘要： There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

    摘要翻译： 在此公开了独特的制造顺序和集成到典型的DRAM沟槽工艺序列中的垂直绝缘体上硅（SOI）双极晶体管的结构。 使用NFET的DRAM阵列允许集成双极NPN序列。 类似地，通过将​​阵列晶体管改变为PFET来实现垂直双极PNP器件。 特别地，在SOI中制造BICMOS器件。 双极发射极触点和CMOS扩散触点同时形成多晶硅插头。 CMOS扩散触点是从存储单元的位线到存储节点的插头触点。

    Very low power logic circuit family with enhanced noise immunity
    9.
    发明授权
    Very low power logic circuit family with enhanced noise immunity 有权
    超低功耗逻辑电路系列，具有增强的抗噪声能力

    公开(公告)号：US6111425A

    公开(公告)日：2000-08-29

    申请号：US173436

    申请日：1998-10-15

    申请人： Claude L. Bertin ,  Russell J. Houghton ,  Wilbur D. Pricer ,  William R. Tonti

    发明人： Claude L. Bertin ,  Russell J. Houghton ,  Wilbur D. Pricer ,  William R. Tonti

    IPC分类号： H03K19/003 ,  H03K3/356 ,  H03K19/173 ,  H03K17/16

    CPC分类号： H03K3/356113 ,  H03K19/1738

    摘要： A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.

    摘要翻译： 一个非常低功率的逻辑电路系列，有利地提供1）保持高性能，2）显着降低的功耗，和3）增强的抗噪声能力。 在第一组实施例中，使用双轨互补逻辑信号来提高对外部噪声的电路抗扰性并且减少由逻辑电路本身产生的噪声。 本发明的接收机部分包括具有两个门到两个源的交叉耦合的两个输入FET。 在一个优选实施例中，接收器和驱动器部分都连接在具有所有N个通道驱动器的中继器中。 第二组实施例在不平衡接收机中具有单侧输入，包括到栅极N沟道的交叉耦合源极和栅极P沟道输出晶体管的交叉耦合漏极。

    Control of hysteresis characteristic within a CMOS differential receiver
    10.
    发明授权
    Control of hysteresis characteristic within a CMOS differential receiver 有权
    控制CMOS差分接收器内的滞后特性

    公开(公告)号：US06281731B1

    公开(公告)日：2001-08-28

    申请号：US09428639

    申请日：1999-10-27

    申请人： John A. Fifield ,  Russell J. Houghton ,  Wilbur D. Pricer ,  William R. Tonti

    发明人： John A. Fifield ,  Russell J. Houghton ,  Wilbur D. Pricer ,  William R. Tonti

    IPC分类号： H03K3297

    CPC分类号： H03K3/3565 ,  H03K3/02337

    摘要： A differential receiver has a switching point accurately set according to a reference voltage, which switching point is dynamically modified, that is, dc hysteresis is provided, by a circuit internal to the differential receiver. Positioning of the resultant hysteresis characteristic about the reference signal is adjusted by establishing a backgate voltage differential between an input transistor and a reference transistor of the differential receiver. A switching circuit is also provided for controlling switching of a hysteresis circuit at the reference signal plus or minus a desired offset. The switching circuit is gated by an output signal of the input transistor.

    摘要翻译： 差分接收器具有根据参考电压精确设置的开关点，通过差分接收器内部的电路动态地修改切换点，即提供直流滞后。 通过在差分接收器的输入晶体管和参考晶体管之间建立背栅电压差来调整所产生的关于参考信号的滞后特性的定位。 还提供了一种开关电路，用于控制滞后电路在参考信号加或减所需偏移的切换。 开关电路由输入晶体管的输出信号选通。