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    Structures and methods of anti-fuse formation in SOI
    1.
    发明授权
    Structures and methods of anti-fuse formation in SOI 失效
    SOI中抗熔丝形成的结构和方法

    公开(公告)号：US06972220B2

    公开(公告)日：2005-12-06

    申请号：US10366298

    申请日：2003-02-12

    申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12 ,  H01L21/00

    CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

    摘要翻译： 可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的反熔丝结构形成在复合衬底上，例如绝缘体上硅 通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。 反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。 绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。 由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。 因此实现了自动修复而不中断操作的可能性。

    Method of forming connection and anti-fuse in layered substrate such as SOI
    3.
    发明授权
    Method of forming connection and anti-fuse in layered substrate such as SOI 有权
    在诸如SOI的层状衬底中形成连接和反熔丝的方法

    公开(公告)号：US07226816B2

    公开(公告)日：2007-06-05

    申请号：US11055106

    申请日：2005-02-11

    申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

    摘要翻译： 可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的抗熔丝结构形成在复合衬底上，例如绝缘体上硅 通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。 反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。 绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。 由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。 因此实现了自动修复而不中断操作的可能性。

    Method for novel SOI DRAM BICMOS NPN
    6.
    发明授权
    Method for novel SOI DRAM BICMOS NPN 失效
    新型SOI DRAM BICMOS NPN的方法

    公开(公告)号：US06492211B1

    公开(公告)日：2002-12-10

    申请号：US09656819

    申请日：2000-09-07

    申请人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

    发明人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

    IPC分类号： H01L2100

    CPC分类号： H01L27/10894 ,  G11C7/065 ,  G11C2207/005 ,  G11C2207/065 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/10897 ,  H01L27/1203

    摘要： There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

    摘要翻译： 在此公开了独特的制造顺序和集成到典型的DRAM沟槽工艺序列中的垂直绝缘体上硅（SOI）双极晶体管的结构。 使用NFET的DRAM阵列允许集成双极NPN序列。 类似地，通过将​​阵列晶体管改变为PFET来实现垂直双极PNP器件。 特别地，在SOI中制造BICMOS器件。 双极发射极触点和CMOS扩散触点同时形成多晶硅插头。 CMOS扩散触点是从存储单元的位线到存储节点的插头触点。

    Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion
    7.
    发明授权
    Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion 失效
    用于使用受控栅极耗尽的CMOS器件形成混合高压（HV / LV）晶体管的方法

    公开(公告)号：US06436749B1

    公开(公告)日：2002-08-20

    申请号：US09658655

    申请日：2000-09-08

    申请人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

    发明人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

    IPC分类号： H01L218238

    CPC分类号： H01L27/092 ,  H01L21/823842

    摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.

    摘要翻译： 公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。 在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。 阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。 因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。

    Electrically programmable antifuses and methods for forming the same
    8.
    发明授权
    Electrically programmable antifuses and methods for forming the same 有权
    电子可编程反熔丝及其形成方法

    公开(公告)号：US06388305B1

    公开(公告)日：2002-05-14

    申请号：US09466495

    申请日：1999-12-17

    申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

    发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

    IPC分类号： H01L2900

    CPC分类号： H01L21/763 ,  H01L23/5252 ,  H01L27/10861 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location.

    摘要翻译： 首先，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该第一导电类型的半导体衬底包括在衬底的表面下面的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。 沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。 第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。 第二次，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该半导体衬底包括形成在衬底的表面中的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。 沟槽包括内表面，衬在内表面的第一电介质材料和填充衬里沟槽的第二电介质材料。 第二逻辑元件还包括形成在第一层的一部分上并且在合并位置处接触衬套在沟槽上的第一介电材料的电介质层; 以及在电介质层和填充沟槽的一部分上延伸的电极。 第二逻辑元件被配置为使得施加在电极和第一层之间的预定电压或更高的电压导致合并位置附近的击穿。

    Single-ended semiconductor receiver with built in threshold voltage difference
    9.
    发明授权
    Single-ended semiconductor receiver with built in threshold voltage difference 失效
    单端半导体接收器内置阈值电压差

    公开(公告)号：US06222395B1

    公开(公告)日：2001-04-24

    申请号：US09225112

    申请日：1999-01-04

    申请人： Claude L. Bertin ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G05F110

    CPC分类号： G05F3/205

    摘要： A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.

    摘要翻译： 一种差分接收器，用于通过使用通过差分对间隔晶体管之间的阈值电压差而获得的内置参考电压来感测小输入电压摆幅。 阈值电压的差异可以通过使用相同材料的晶体管对的栅极的离子注入的不同值，或通过使用不同材料的剂量来产生。 也可以通过使用不同的晶体管沟道长度来获得阈值电压的差异。 也可以通过使用电压控制衬底装置控制晶体管衬底电压来调制阈值电压。

    High frequency valid data strobe
    10.
    发明授权
    High frequency valid data strobe 失效
    高频有效数据选通

    公开(公告)号：US06177807B1

    公开(公告)日：2001-01-23

    申请号：US09322465

    申请日：1999-05-28

    申请人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G03K1716

    CPC分类号： G06F13/4086 ,  H03K5/06 ,  H04L25/0298

    摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.

    摘要翻译： 具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。 数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。 具有递增可变长度的传输线短截线连接到控制线14的存储器控​​制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路 在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。