利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

47 条记录 (耗时 0.023 秒)

    Methods of forming semiconductor constructions
    2.
    发明申请
    Methods of forming semiconductor constructions 有权
    形成半导体结构的方法

    公开(公告)号：US20070238295A1

    公开(公告)日：2007-10-11

    申请号：US11402659

    申请日：2006-04-11

    申请人： Ramakanth Alapati ,  Ardavan Niroomand ,  Gurtej Sandhu ,  Luan Tran

    发明人： Ramakanth Alapati ,  Ardavan Niroomand ,  Gurtej Sandhu ,  Luan Tran

    IPC分类号： H01L21/302 ,  H01L21/31

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/76232 ,  H01L27/105 ,  H01L27/1052

    摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.

    摘要翻译： 本发明包括形成用于半导体结构的隔离区域的方法。 可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。 可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。 第一个开口用含碳材料的共形层变窄。 穿过保形层以沿着狭窄的开口的底部露出衬底。 去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。 然后从第一开口内去除含碳材料，并且在第一和第二开口内形成电绝缘材料。 电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

    PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES
    4.
    发明申请
    PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 失效
    相对于光刻特征的PITCH减少图案

    公开(公告)号：US20070161251A1

    公开(公告)日：2007-07-12

    申请号：US11681027

    申请日：2007-03-01

    申请人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    发明人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

    摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

    摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

    Pitch reduced patterns relative to photolithography features
    5.
    发明申请
    Pitch reduced patterns relative to photolithography features 有权
    相对于光刻特征的间距减小

    公开(公告)号：US20060211260A1

    公开(公告)日：2006-09-21

    申请号：US11214544

    申请日：2005-08-29

    申请人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    发明人： Luan Tran ,  William Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer Abatchev ,  Gurtej Sandhu ,  D. Durcan

    IPC分类号： H01L21/31

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

    摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

    摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

    Nano-crystal etch process
    8.
    发明授权
    Nano-crystal etch process 有权
    纳米晶体蚀刻工艺

    公开(公告)号：US08809198B2

    公开(公告)日：2014-08-19

    申请号：US12650029

    申请日：2009-12-30

    申请人： Ramakanth Alapati ,  Paul Morgan ,  Max Hineman

    发明人： Ramakanth Alapati ,  Paul Morgan ,  Max Hineman

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32134 ,  B82Y10/00 ,  H01L21/28273

    摘要： A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.

    摘要翻译： 一种用于在绝缘层上选择性去除纳米晶体的方法。 该方法包括在其上提供具有纳米晶体的绝缘层; 将纳米晶体暴露于包含游离基氯源，离子氯或二者的高密度等离子体，以修饰纳米晶体; 并用湿蚀刻剂去除修饰的纳米晶体。

    Simplified pitch doubling process flow
    10.
    发明授权
    Simplified pitch doubling process flow 有权
    简化俯仰加倍流程

    公开(公告)号：US08338959B2

    公开(公告)日：2012-12-25

    申请号：US13229898

    申请日：2011-09-12

    申请人： Ardavan Niroomand ,  Baosuo Zhou ,  Ramakanth Alapati

    发明人： Ardavan Niroomand ,  Baosuo Zhou ,  Ramakanth Alapati

    IPC分类号： H01L23/48

    CPC分类号： H01L27/04 ,  H01L21/0338 ,  H01L21/3088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

    摘要翻译： 一种用于制造半导体器件的方法包括对一层光致抗蚀剂材料进行构图以形成多个心轴。 该方法还包括通过原子层沉积（ALD）工艺在多个心轴上沉积氧化物材料。 该方法还包括从暴露的水平表面各向异性地蚀刻氧化物材料。 该方法还包括选择性地蚀刻光刻胶材料。