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    Encryption key for multi-key encryption in programmable logic device
    6.
    发明授权
    Encryption key for multi-key encryption in programmable logic device 有权
    可编程逻辑器件中多键加密的加密密钥

    公开(公告)号：US06957340B1

    公开(公告)日：2005-10-18

    申请号：US09724873

    申请日：2000-11-28

    申请人： Raymond C. Pang ,  Stephen M. Trimberger ,  Jennifer Wong

    发明人： Raymond C. Pang ,  Stephen M. Trimberger ,  Jennifer Wong

    IPC分类号： G06F21/00 ,  H04L9/00 ,  H04L9/14

    CPC分类号： G06F21/76 ,  H04L9/0637 ,  H04L9/0894 ,  H04L9/14

    摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.

    摘要翻译： 有时期望保护PLD中使用的设计不被复制。 如果设计存储在与PLD不同的设备中并通过比特流读入PLD，则在加载时可以观察和复制未加密的比特流。 根据本发明，用于配置具有加密设计的PLD的比特流包括用于控制配置比特流的加载的未加密的字和实际指定设计的加密的字。

    Programmable logic device with decryption and structure for preventing design relocation
    7.
    发明授权
    Programmable logic device with decryption and structure for preventing design relocation 有权
    具有解密和结构的可编程逻辑器件，用于防止设计重新定位

    公开(公告)号：US07117372B1

    公开(公告)日：2006-10-03

    申请号：US09724972

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    IPC分类号： H04L9/14 ,  H04K1/00

    CPC分类号： G01R31/31719 ,  G06F12/1408 ,  G06F21/76 ,  H04L9/0625 ,  H04L9/0637

    摘要： It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.

    摘要翻译： 有时期望保护PLD中使用的设计不被复制。 根据本发明，设计被加密，然后加载到PLD中，然后解密，然后加载到PLD的配置存储器中。 攻击者可以将设计重新定位到PLD的可见部分，并学习设计。 本发明通过将地址信息附加到加密密钥或通过加密设计要加载的地址以及加密设计本身来防止设计重定位。 因此，如果攻击者试图将设计加载到PLD的不同部分，则加密的设计将无法正确解密。

    Clock-gating circuit for reducing power consumption
    8.
    发明授权
    Clock-gating circuit for reducing power consumption 有权
    时钟门控电路，用于降低功耗

    公开(公告)号：US06204695B1

    公开(公告)日：2001-03-20

    申请号：US09336357

    申请日：1999-06-18

    申请人： Peter H. Alfke ,  Alvin Y. Ching ,  Scott O. Frake ,  Jennifer Wong ,  Steven P. Young

    发明人： Peter H. Alfke ,  Alvin Y. Ching ,  Scott O. Frake ,  Jennifer Wong ,  Steven P. Young

    IPC分类号： H03H19096

    CPC分类号： G06F1/10

    摘要： A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

    摘要翻译： 为逻辑器件提供时钟选通电路，可降低器件资源需求，消除用户定义自己的时钟选通电路的需要，并消除不期望的时钟信号干扰，如毛刺和欠压脉冲。 在一个实施例中，时钟选通电路包括用于接收输入时钟信号的输入端; 用于接收时钟使能信号的输入端; 存储锁存器，其耦合以接收所述输入时钟信号和所述时钟使能信号，并且作为响应，提供时钟门控制信号; 以及耦合以接收输入时钟信号和时钟门控制信号的逻辑门。 逻辑门选择地响应于时钟门控制信号路由输入时钟信号，由此提供输出时钟信号。

    Method of time multiplexing a programmable logic device
    9.
    发明授权
    Method of time multiplexing a programmable logic device 有权
    时间复用可编程逻辑器件的方法

    公开(公告)号：US06480954B2

    公开(公告)日：2002-11-12

    申请号：US09876745

    申请日：2001-06-06

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G06F900

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

    摘要翻译： 可编程逻辑器件（PLD）包括至少一个可配置元件和用于配置可配置元件的多个可编程逻辑元件。 或者，PLD包括用于配置互连结构的互连结构和多个可编程逻辑元件。 在任一实施例中，至少一个可编程逻辑元件包括N个存储器单元。 N个存储器单元中的预定的一个形成存储器片的一部分，其中可编程逻辑器件的每个片的至少一部分被分配给配置数据或用户数据存储器。 通常，一个存储器片提供可编程逻辑器件的一个配置。 根据一个实施例，存储器访问端口耦合在N个存储器单元中的至少一个和任一个可配置元件或互连之间，从而有助于在一个配置期间将新的配置数据加载到其他存储器片段中。 新的配置数据可以包括片外或片上数据。 本发明通常将至少一个片分配给用户数据存储器，并且包括用于禁止对N个存储器单元中的至少一个的访问的装置。

    Method of time multiplexing a programmable logic device
    10.
    发明授权
    Method of time multiplexing a programmable logic device 失效
    时间复用可编程逻辑器件的方法

    公开(公告)号：US5629637A

    公开(公告)日：1997-05-13

    申请号：US517017

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17752 ,  H03K19/17704 ,  H03K19/17756

    摘要： A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element. Further alternatively, if the PLD includes a plurality of combinational logic elements and a plurality of sequential logic elements, the method further includes scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to the sequential logic element and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that the sequential logic element drives. If the PLD includes a plurality of combinational logic elements, a plurality of sequential logic elements, and a storage device, the method further includes mapping at least one of the sequential logic elements in the design into the storage device and scheduling the plurality of combinational logic elements and the remaining sequential logic elements.

    摘要翻译： 一种时间复用可编程逻辑器件（PLD）的方法包括输入PLD的设计并将设计逻辑的评估分成多个微循环。 该方法还包括识别不在设计的关键路径内的逻辑，并重新安排所识别的逻辑以在其它微循环中进行评估。 或者，如果PLD包括多个组合逻辑元件，则该方法还包括在不早于生成到所述组合逻辑元件的输入信号的所有组合逻辑元件的微循环中调度组合逻辑元件。 此外，如果PLD包括多个组合逻辑元件和多个顺序逻辑元件，则该方法还包括在不早于生成到顺序逻辑的输入信号的所有组合逻辑元件的微循环中调度顺序逻辑元件 元素，并且在不超过所有组合逻辑元件或顺序逻辑元件驱动的顺序逻辑元件的微循环中调度每个顺序逻辑元件。 如果PLD包括多个组合逻辑元件，多个顺序逻辑元件和存储装置，则该方法还包括将设计中的顺序逻辑元件中的至少一个映射到存储装置中并调度多个组合逻辑 元素和剩余的顺序逻辑元素。