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34 条记录 (耗时 0.031 秒)

    Programmable logic device with decryption and structure for preventing design relocation
    3.
    发明授权
    Programmable logic device with decryption and structure for preventing design relocation 有权
    具有解密和结构的可编程逻辑器件，用于防止设计重新定位

    公开(公告)号：US07117372B1

    公开(公告)日：2006-10-03

    申请号：US09724972

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    IPC分类号： H04L9/14 ,  H04K1/00

    CPC分类号： G01R31/31719 ,  G06F12/1408 ,  G06F21/76 ,  H04L9/0625 ,  H04L9/0637

    摘要： It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.

    摘要翻译： 有时期望保护PLD中使用的设计不被复制。 根据本发明，设计被加密，然后加载到PLD中，然后解密，然后加载到PLD的配置存储器中。 攻击者可以将设计重新定位到PLD的可见部分，并学习设计。 本发明通过将地址信息附加到加密密钥或通过加密设计要加载的地址以及加密设计本身来防止设计重定位。 因此，如果攻击者试图将设计加载到PLD的不同部分，则加密的设计将无法正确解密。

    Encryption key for multi-key encryption in programmable logic device
    5.
    发明授权
    Encryption key for multi-key encryption in programmable logic device 有权
    可编程逻辑器件中多键加密的加密密钥

    公开(公告)号：US06957340B1

    公开(公告)日：2005-10-18

    申请号：US09724873

    申请日：2000-11-28

    申请人： Raymond C. Pang ,  Stephen M. Trimberger ,  Jennifer Wong

    发明人： Raymond C. Pang ,  Stephen M. Trimberger ,  Jennifer Wong

    IPC分类号： G06F21/00 ,  H04L9/00 ,  H04L9/14

    CPC分类号： G06F21/76 ,  H04L9/0637 ,  H04L9/0894 ,  H04L9/14

    摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.

    摘要翻译： 有时期望保护PLD中使用的设计不被复制。 如果设计存储在与PLD不同的设备中并通过比特流读入PLD，则在加载时可以观察和复制未加密的比特流。 根据本发明，用于配置具有加密设计的PLD的比特流包括用于控制配置比特流的加载的未加密的字和实际指定设计的加密的字。

    Structure and method for loading encryption keys through a test access port
    7.
    发明授权
    Structure and method for loading encryption keys through a test access port 有权
    通过测试访问端口加载加密密钥的结构和方法

    公开(公告)号：US06965675B1

    公开(公告)日：2005-11-15

    申请号：US09724865

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  John M. Thendean

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  John M. Thendean

    IPC分类号： G06F21/00 ,  H04L9/08

    CPC分类号： G06F21/76 ,  H04L9/0637 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/34

    摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being written into the PLD. It is desirable that decryption keys be stored within the PLD, and that they be loaded conveniently before a board including the PLD is sold. The invention allows the PLD to be placed into a printed circuit board and the board to be tested using a JTAG port of the PLD, and then allows the decryption keys to be loaded into a key memory using the JTAG port. Loading of the keys can be performed without also loading of a design into the PLD. Loading may be performed without the use of a device programmer.

    摘要翻译： 有时需要加密设计以加载到PLD中，以便攻击者可能不会在将设计写入PLD时学习和复制设计。 希望解密密钥存储在PLD中，并且在出售包括PLD的板之前方便地加载它们。 本发明允许使用PLD的JTAG端口将PLD放入印刷电路板和要测试的板，然后使用JTAG端口将解密密钥加载到密钥存储器中。 可以在不将设计加载到PLD中的情况下执行加载键。 可以在不使用设备编程器的情况下执行加载。

    Partially encrypted bitstream method
    8.
    发明授权
    Partially encrypted bitstream method 失效
    部分加密比特流方法

    公开(公告)号：US07058177B1

    公开(公告)日：2006-06-06

    申请号：US09724974

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze

    IPC分类号： H04L9/00

    CPC分类号： G06F21/76 ,  H04L9/0637 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/34

    摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, a method for generating a bitstream for storing an encrypted design begins by generating an unencrypted bitstream including bits representing the design and bits that control loading of the design. The bits representing the design are encrypted and are combined with the bits that control loading, which are not encrypted.

    摘要翻译： 有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。 根据本发明，用于生成用于存储加密设计的比特流的方法开始于生成一个未加密比特流，包括表示设计的比特和控制加载设计的比特。 表示设计的位被加密，并且与控制加载的位组合，这些位未被加密。

    Digital clock manager having cascade voltage switch logic clock paths
    9.
    发明授权
    Digital clock manager having cascade voltage switch logic clock paths 有权
    数字时钟管理器具有级联电压开关逻辑时钟路径

    公开(公告)号：US07038519B1

    公开(公告)日：2006-05-02

    申请号：US10837324

    申请日：2004-04-30

    申请人： Raymond C. Pang ,  Jennifer Wong

    发明人： Raymond C. Pang ,  Jennifer Wong

    IPC分类号： H03H11/26

    CPC分类号： H03K19/1738 ,  H03H11/26 ,  H03K2005/00195 ,  H03K2005/00228 ,  H03K2005/00234

    摘要： A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.

    摘要翻译： 提供具有差分时钟信号路径的数字时钟管理器。 差分时钟信号路径通过用传统数字时钟管理器的单端电路元件替代对称级联电压开关逻辑（CVSL）电路元件来提供，包括CVSL延迟缓冲器，CVSL多路复用器，CVSL与门，CVSL或门和CVSL组 - 锁存器。 这些对称的CVSL与门，CVSL或门和CVSL设置复位锁存器代表新的电路元件。