-
公开(公告)号：US06981153B1
公开(公告)日：2005-12-27
申请号：US09724975
申请日：2000-11-28
CPC分类号： H04N21/23476 , G06F17/5054 , G06F21/76
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD before being loaded into configuration memory cells for configuring the PLD. According to the invention, in such a device, a method is provided to prevent the design from being read back from the PLD in its decrypted state if it had been encrypted when loaded into the PLD.
摘要翻译： 有时期望保护PLD中使用的设计不被复制。 如果设计存储在与PLD不同的设备中并且通过比特流读入PLD，则在加载到用于配置PLD的配置存储器单元之前，设计可以在PLD中被读入PLD并被解密并被解密。 根据本发明，在这种设备中，提供了一种方法，用于防止在被加载到PLD中时将设计从PLD解密的状态下读回PLD。
-
公开(公告)号：US07117373B1
公开(公告)日：2006-10-03
申请号：US09724734
申请日：2000-11-28
IPC分类号： G06F11/30 , G06F12/14 , H04L9/32 , G06F7/38 , H03K19/177
CPC分类号： H04L9/12 , G06F21/76 , H04L9/0637 , H04L9/0894 , H04L2209/12 , H04L2209/34
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.
摘要翻译： 有时期望保护PLD中使用的设计不被复制。 如果设计存储在与PLD不同的设备中并通过比特流读入PLD，则在加载时可以观察和复制未加密的比特流。 根据本发明，用于配置具有加密设计的PLD的比特流包括用于控制配置比特流的加载的未加密的字和实际指定设计的加密的字。
-
3.发明授权Programmable logic device with decryption and structure for preventing design relocation 有权具有解密和结构的可编程逻辑器件，用于防止设计重新定位公开(公告)号：US07117372B1
公开(公告)日：2006-10-03
申请号：US09724972
申请日：2000-11-28
CPC分类号： G01R31/31719 , G06F12/1408 , G06F21/76 , H04L9/0625 , H04L9/0637
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.
摘要翻译： 有时期望保护PLD中使用的设计不被复制。 根据本发明，设计被加密，然后加载到PLD中，然后解密，然后加载到PLD的配置存储器中。 攻击者可以将设计重新定位到PLD的可见部分，并学习设计。 本发明通过将地址信息附加到加密密钥或通过加密设计要加载的地址以及加密设计本身来防止设计重定位。 因此，如果攻击者试图将设计加载到PLD的不同部分，则加密的设计将无法正确解密。
-
4.发明授权公开(公告)号：US06931543B1
公开(公告)日：2005-08-16
申请号：US09724652
申请日：2000-11-28
申请人： Raymond C. Pang , Walter N. Sze , Jennifer Wong , Stephen M. Trimberger , John M. Thendean , Kameswara K. Rao
发明人： Raymond C. Pang , Walter N. Sze , Jennifer Wong , Stephen M. Trimberger , John M. Thendean , Kameswara K. Rao
CPC分类号： H04N21/23476 , G06F21/76 , G06F2221/2107
摘要： To prevent copying of a design implemented in a programmable logic device (PLD), the PLD itself stores a decryption key or keys loaded by the designer, and includes a decryptor for decrypting an encrypted configuration bitstream as it is loaded into the PLD. The PLD also includes logic for reading header information that indicates whether the bitstream is encrypted, and can accept both encrypted and unencrypted bitstreams. The encryption keys may be stored in non-volatile memory or backed up with a battery so that they are retained when power is removed.
摘要翻译： 为了防止在可编程逻辑器件（PLD）中实现的设计的复制，PLD本身存储由设计者加载的解密密钥或密钥，并且包括解密器，用于在加载到PLD中时对加密的配置比特流进行解密。 PLD还包括用于读取标题信息的逻辑，其指示比特流是否被加密，并且可以接受加密和未加密的比特流。 加密密钥可以存储在非易失性存储器中或用电池备份，以便在掉电时保留加密密钥。
-
公开(公告)号：US06957340B1
公开(公告)日：2005-10-18
申请号：US09724873
申请日：2000-11-28
CPC分类号： G06F21/76 , H04L9/0637 , H04L9/0894 , H04L9/14
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.
摘要翻译： 有时期望保护PLD中使用的设计不被复制。 如果设计存储在与PLD不同的设备中并通过比特流读入PLD，则在加载时可以观察和复制未加密的比特流。 根据本发明，用于配置具有加密设计的PLD的比特流包括用于控制配置比特流的加载的未加密的字和实际指定设计的加密的字。
-
公开(公告)号：US06366117B1
公开(公告)日：2002-04-02
申请号：US09724973
申请日：2000-11-28
申请人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
发明人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
IPC分类号： H04L900
CPC分类号： G06F21/76
摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.
摘要翻译： 有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。 根据本发明，加密设计由PLD内的密钥或密钥解密，当通过存储在非易失性存储器中的电力被去除或通过在电力被从 PLD。
-
公开(公告)号：US06480954B2
公开(公告)日：2002-11-12
申请号：US09876745
申请日：2001-06-06
IPC分类号： G06F900
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
摘要翻译： 可编程逻辑器件（PLD）包括至少一个可配置元件和用于配置可配置元件的多个可编程逻辑元件。 或者，PLD包括用于配置互连结构的互连结构和多个可编程逻辑元件。 在任一实施例中，至少一个可编程逻辑元件包括N个存储器单元。 N个存储器单元中的预定的一个形成存储器片的一部分，其中可编程逻辑器件的每个片的至少一部分被分配给配置数据或用户数据存储器。 通常，一个存储器片提供可编程逻辑器件的一个配置。 根据一个实施例，存储器访问端口耦合在N个存储器单元中的至少一个和任一个可配置元件或互连之间，从而有助于在一个配置期间将新的配置数据加载到其他存储器片段中。 新的配置数据可以包括片外或片上数据。 本发明通常将至少一个片分配给用户数据存储器，并且包括用于禁止对N个存储器单元中的至少一个的访问的装置。
-
公开(公告)号：US5629637A
公开(公告)日：1997-05-13
申请号：US517017
申请日：1995-08-18
IPC分类号： H03K19/177
CPC分类号： H03K19/17752 , H03K19/17704 , H03K19/17756
摘要： A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element. Further alternatively, if the PLD includes a plurality of combinational logic elements and a plurality of sequential logic elements, the method further includes scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to the sequential logic element and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that the sequential logic element drives. If the PLD includes a plurality of combinational logic elements, a plurality of sequential logic elements, and a storage device, the method further includes mapping at least one of the sequential logic elements in the design into the storage device and scheduling the plurality of combinational logic elements and the remaining sequential logic elements.
摘要翻译： 一种时间复用可编程逻辑器件（PLD）的方法包括输入PLD的设计并将设计逻辑的评估分成多个微循环。 该方法还包括识别不在设计的关键路径内的逻辑，并重新安排所识别的逻辑以在其它微循环中进行评估。 或者，如果PLD包括多个组合逻辑元件，则该方法还包括在不早于生成到所述组合逻辑元件的输入信号的所有组合逻辑元件的微循环中调度组合逻辑元件。 此外，如果PLD包括多个组合逻辑元件和多个顺序逻辑元件，则该方法还包括在不早于生成到顺序逻辑的输入信号的所有组合逻辑元件的微循环中调度顺序逻辑元件 元素，并且在不超过所有组合逻辑元件或顺序逻辑元件驱动的顺序逻辑元件的微循环中调度每个顺序逻辑元件。 如果PLD包括多个组合逻辑元件，多个顺序逻辑元件和存储装置，则该方法还包括将设计中的顺序逻辑元件中的至少一个映射到存储装置中并调度多个组合逻辑 元素和剩余的顺序逻辑元素。
-
公开(公告)号：US5784313A
公开(公告)日：1998-07-21
申请号：US516808
申请日：1995-08-18
IPC分类号： G06F17/50 , G11C5/00 , H03K19/177 , G11C13/00
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
-
公开(公告)号：US5978260A
公开(公告)日：1999-11-02
申请号：US119534
申请日：1998-07-20
IPC分类号： G06F17/50 , G11C5/00 , H03K19/177 , G11C13/00
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
-
-
-
-
-
-
-
-
-
搜索结果
72 条记录 (耗时 0.035 秒)
