利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.026 秒)

    Programmable logic device with decryption and structure for preventing design relocation
    4.
    发明授权
    Programmable logic device with decryption and structure for preventing design relocation 有权
    具有解密和结构的可编程逻辑器件，用于防止设计重新定位

    公开(公告)号：US07117372B1

    公开(公告)日：2006-10-03

    申请号：US09724972

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    IPC分类号： H04L9/14 ,  H04K1/00

    CPC分类号： G01R31/31719 ,  G06F12/1408 ,  G06F21/76 ,  H04L9/0625 ,  H04L9/0637

    摘要： It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.

    摘要翻译： 有时期望保护PLD中使用的设计不被复制。 根据本发明，设计被加密，然后加载到PLD中，然后解密，然后加载到PLD的配置存储器中。 攻击者可以将设计重新定位到PLD的可见部分，并学习设计。 本发明通过将地址信息附加到加密密钥或通过加密设计要加载的地址以及加密设计本身来防止设计重定位。 因此，如果攻击者试图将设计加载到PLD的不同部分，则加密的设计将无法正确解密。

    Partially encrypted bitstream method
    5.
    发明授权
    Partially encrypted bitstream method 失效
    部分加密比特流方法

    公开(公告)号：US07058177B1

    公开(公告)日：2006-06-06

    申请号：US09724974

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze

    IPC分类号： H04L9/00

    CPC分类号： G06F21/76 ,  H04L9/0637 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/34

    摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, a method for generating a bitstream for storing an encrypted design begins by generating an unencrypted bitstream including bits representing the design and bits that control loading of the design. The bits representing the design are encrypted and are combined with the bits that control loading, which are not encrypted.

    摘要翻译： 有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。 根据本发明，用于生成用于存储加密设计的比特流的方法开始于生成一个未加密比特流，包括表示设计的比特和控制加载设计的比特。 表示设计的位被加密，并且与控制加载的位组合，这些位未被加密。

    Dummy block replacement for logic simulation
    6.
    发明授权
    Dummy block replacement for logic simulation 失效
    用于逻辑模拟的虚拟块替换

    公开(公告)号：US07330808B1

    公开(公告)日：2008-02-12

    申请号：US10627335

    申请日：2003-07-24

    申请人： Vincent J. Jorgensen ,  Walter N. Sze

    发明人： Vincent J. Jorgensen ,  Walter N. Sze

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： A method (10) of reducing a size of a netlist for a target architecture can include the steps of creating (12) a netlist of objects for the target architecture, identifying (14) objects specific to the target architecture that are repeated regularly to identify potential dummy objects, creating (15) a list of objects used by a design in the target architecture, and forming (16) a list of unused objects in the target architecture from the netlist of objects and the list of objects used by the design. The method can further include the steps of replacing (18) at least one object in the list of unused objects with an appropriate dummy object to form a modified netlist and simulating (19) the modified netlist.

    摘要翻译： 减少目标架构的网表的大小的方法（10）可以包括以下步骤：创建（12）目标架构的对象的网表，识别（14）定期重复的目标架构特有的对象以识别 潜在的虚拟对象，创建（15）目标架构中的设计使用的对象的列表，以及从对象的网表和设计使用的对象的列表中形成（16）目标体系结构中的未使用对象的列表。 该方法还可以包括以下步骤：用适当的虚拟对象来替换（18）未使用对象列表中的至少一个对象，以形成修改的网表并模拟（19）修改的网表。

    Verifying configuration memory of a programmable logic device
    7.
    发明授权
    Verifying configuration memory of a programmable logic device 有权
    验证可编程逻辑器件的配置存储器

    公开(公告)号：US07912693B1

    公开(公告)日：2011-03-22

    申请号：US12113363

    申请日：2008-05-01

    申请人： Ui Sun Han ,  Walter N. Sze ,  Tsu-Chien Shen

    发明人： Ui Sun Han ,  Walter N. Sze ,  Tsu-Chien Shen

    IPC分类号： G06F17/50 ,  G06F9/00

    CPC分类号： G06F17/5022 ,  G06F17/5027

    摘要： Systems and methods are provided for verifying respective configuration data values for programming configuration memory cells of an integrated circuit device such as a programmable logic device (PLD). Each configuration memory cell controls an input of a corresponding initialization value from a file in response to a selectable assertion of an initialization signal of a test bench during a logic simulation of the PLD. The file structurally associates the configuration memory cell with the corresponding initialization value. A current value of one or more of the configuration memory cells is written with the respective configuration data value via a configuration port of the PLD during the logic simulation. Each configuration memory cell compares its initialization and current values in response to a selectable assertion of a check signal of the test bench. A mismatch error is output in response to a difference between the initialization and current values of one or more of the configuration memory cells.

    摘要翻译： 提供了用于验证用于编程诸如可编程逻辑器件（PLD）的集成电路器件的配置存储器单元的相应配置数据值的系统和方法。 响应于在PLD的逻辑模拟期间对测试台的初始化信号的选择性断言，每个配置存储单元控制来自文件的相应初始化值的输入。 该文件结构地将配置存储单元与相应的初始化值相关联。 在逻辑模拟期间，通过PLD的配置端口，通过相应的配置数据值写入一个或多个配置存储器单元的当前值。 每个配置存储器单元响应于可选择地确定测试台的检查信号来比较其初始化和当前值。 响应于一个或多个配置存储器单元的初始化和当前值之间的差异而输出不匹配错误。

    System and method for testing of interconnects in a programmable logic device
    8.
    发明授权
    System and method for testing of interconnects in a programmable logic device 有权
    用于在可编程逻辑器件中测试互连的系统和方法

    公开(公告)号：US07509547B1

    公开(公告)日：2009-03-24

    申请号：US11220924

    申请日：2005-09-07

    申请人： Ui Sun Han ,  Walter N. Sze

    发明人： Ui Sun Han ,  Walter N. Sze

    IPC分类号： G01R31/28 ,  G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G11C29/00 ,  G06F17/50 ,  G06F9/45 ,  G06F9/455 ,  H03K17/693 ,  H03K19/00

    CPC分类号： G11C29/02 ,  G01R31/31717 ,  G01R31/318516 ,  G11C29/025

    摘要： Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the interconnects are read from a database for the PLD. For each interconnect, a respective test design is automatically generated with the test design replacing a portion of a coupling between an input pad and an output pad in an archetypal test design with a coupling that includes the interconnect. A respective configuration is automatically generated for the PLD from each test design. A respective operation of the PLD programmed with each configuration is simulated, and each operation of the PLD for is checked inconsistency with an expected result. In response to any inconsistency, an indication of the inconsistency is displayed to a user.

    摘要翻译： 方法和系统为可编程逻辑器件（PLD）和相关软件工具的互连中的缺陷提供早期和简化的测试。 描述互连的数据从PLD的数据库读取。 对于每个互连，通过测试设计自动生成相应的测试设计，其中使用包括互连的耦合在原型测试设计中替换输入焊盘和输出焊盘之间的耦合的一部分。 针对每个测试设计的PLD自动生成相应的配置。 仿真每个配置编程的PLD的相应操作，并检查PLD的每个操作与预期结果不一致。 响应于任何不一致，向用户显示不一致的指示。