High-energy suppression for capacitor transimpedance amplifier (CTIA)-based imagers or other imaging devices

    公开(公告)号:US11843355B2

    公开(公告)日:2023-12-12

    申请号:US17649994

    申请日:2022-02-04

    申请人: Raytheon Company

    IPC分类号: H03F3/08 H03F1/08 H03F3/70

    CPC分类号: H03F3/087 H03F1/08 H03F3/70

    摘要: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

    HIGH-ENERGY SUPPRESSION FOR CAPACITOR TRANSIMPEDANCE AMPLIFIER (CTIA)-BASED IMAGERS OR OTHER IMAGING DEVICES

    公开(公告)号:US20230253932A1

    公开(公告)日:2023-08-10

    申请号:US17649994

    申请日:2022-02-04

    申请人: Raytheon Company

    IPC分类号: H03F3/08 H03F1/08 H03F3/70

    CPC分类号: H03F3/087 H03F1/08 H03F3/70

    摘要: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

    MOSAIC FOCAL PLANE ARRAY
    4.
    发明申请

    公开(公告)号:US20220310690A1

    公开(公告)日:2022-09-29

    申请号:US17212085

    申请日:2021-03-25

    申请人: Raytheon Company

    摘要: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

    PER-PIXEL DETECTOR BIAS CONTROL
    6.
    发明申请

    公开(公告)号:US20210381888A1

    公开(公告)日:2021-12-09

    申请号:US16892430

    申请日:2020-06-04

    申请人: RAYTHEON COMPANY

    IPC分类号: G01J1/46 G01J5/34

    摘要: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.

    Per-pixel detector bias control
    7.
    发明授权

    公开(公告)号:US11626445B2

    公开(公告)日:2023-04-11

    申请号:US16549069

    申请日:2019-08-23

    申请人: RAYTHEON COMPANY

    摘要: A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

    Per-pixel detector bias control
    9.
    发明授权

    公开(公告)号:US11561132B2

    公开(公告)日:2023-01-24

    申请号:US16892430

    申请日:2020-06-04

    申请人: RAYTHEON COMPANY

    IPC分类号: G01J1/46 G01J5/34 G01J1/44

    摘要: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.

    Pulse-frequency modulation (PFM) digital pixel unit-cell including dual-mode gain selection

    公开(公告)号:US11202021B2

    公开(公告)日:2021-12-14

    申请号:US16697742

    申请日:2019-11-27

    申请人: RAYTHEON COMPANY

    摘要: A digital unit-cell included in an imaging system includes a light sensor configured to generate an electrical charge in response to receiving light, and an energy storage circuit configured to establish a first parasitic capacitance and second large capacitance to store the electrical charge. The digital unit-cell further includes a gain selection circuit and a dual-mode comparator. The gain selection circuit is configured operate in a first mode to invoke the first capacitance and a second mode to invoke the second capacitance. The dual-mode comparator is configured to operate in a first reset mode that generates a first reset signal having a first pulse duration and a second reset mode that generates a second reset signal having a second pulse duration that is a longer than the first pulse duration.