公开(公告)号：US5923211A

公开(公告)日：1999-07-13

申请号：US861039

申请日：1997-05-21

申请人： Reading Maley ,  Albrecht Schoy

发明人： Reading Maley ,  Albrecht Schoy

IPC分类号： G05F1/46 ,  G05F3/24 ,  G05F3/30 ,  G05F3/02

CPC分类号： G05F1/46 ,  G05F3/247 ,  G05F3/30

摘要： A reference voltage generation circuit is provided for use in gate oxide protected circuits for generating an NMOS reference voltage and PMOS reference voltage in which the NMOS reference voltage is independent of an I/O buffer power supply potential and in which the PMOS reference voltage tracks the supply voltage. The reference voltage generation circuit includes a bandgap voltage reference circuit, a first operational amplifier, a voltage divider and a second operational amplifier. In one embodiment, the NMOS reference voltage is approximately +2.2 volts and is referenced with respect to ground. The PMOS reference voltage is approximately +1.1 volts and referenced with respect to the I/O buffer power supply voltage and the NMOS reference voltage.

摘要翻译： 提供参考电压产生电路用于栅极氧化物保护电路，用于产生NMOS参考电压和PMOS参考电压，其中NMOS参考电压独立于I / O缓冲器电源电位，并且其中PMOS参考电压跟踪 电源电压。 参考电压产生电路包括带隙电压参考电路，第一运算放大器，分压器和第二运算放大器。 在一个实施例中，NMOS参考电压大约为+2.2伏，并且相对于地面参考。 PMOS参考电压约为+1.1伏，并参考I / O缓冲器电源电压和NMOS参考电压。

公开(公告)号：US5969542A

公开(公告)日：1999-10-19

申请号：US861038

申请日：1997-05-21

申请人： Reading Maley ,  Albrecht Schoy

发明人： Reading Maley ,  Albrecht Schoy

IPC分类号： H03K3/012 ,  H03K3/356 ,  H03K17/10 ,  H03K19/0185 ,  H03K19/017

CPC分类号： H03K3/012 ,  H03K17/102 ,  H03K3/356147

摘要： An improved gate oxide protected level shifter is provided which has a higher speed of operation than is traditionally available. The level shifter includes a first capacitor coupled between a first output terminal and the input of an inverter and a second capacitor coupled between a first node and the output of the inverter. As a result, the speed of the transitions at the gates of the pair of cross-coupled P-channel MOS transistors is increased several times.

摘要翻译： 提供了一种改进的栅氧化物保护电平转换器，其具有比传统可用的更高的操作速度。 电平移位器包括耦合在第一输出端子和反相器的输入端之间的第一电容器和耦合在第一节点和反相器的输出端之间的第二电容器。 结果，在一对交叉耦合的P沟道MOS晶体管的栅极处的转变速度增加了几倍。

公开(公告)号：US5892371A

公开(公告)日：1999-04-06

申请号：US599878

申请日：1996-02-12

申请人： Reading Maley

发明人： Reading Maley

IPC分类号： H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： An oxide protection circuit prevents failure of the MOS transistors in a digital device. A voltage difference at a gate oxide of a digital device does not exceed a breakdown voltage magnitude. The gate oxide protection circuit includes a plurality of transistors which turn OFF or ON when a node reaches a predetermined voltage of V.sub.refp +V.sub.t or V.sub.refn -V.sub.t, where V.sub.refp and V.sub.refn are reference applied at a gate of a PMOS or an NMOS transistor, and V.sub.t equals a threshold voltage of the MOS transistor.

摘要翻译： 氧化物保护电路防止数字装置中的MOS晶体管的故障。 数字装置的栅极氧化物处的电压差不超过击穿电压的大小。 栅极氧化物保护电路包括多个晶体管，当节点到达预定电压Vrefp + Vt或Vrefn-Vt时，该晶体管截止或导通，其中Vrefp和Vrefn被提供在PMOS或NMOS晶体管的栅极处，以及 Vt等于MOS晶体管的阈值电压。

公开(公告)号：US06744303B1

公开(公告)日：2004-06-01

申请号：US10371944

申请日：2003-02-21

申请人： Reading Maley

发明人： Reading Maley

IPC分类号： G05F110

CPC分类号： G05F1/46

摘要： A method and apparatus for compensating for tunneling leakage current through a first capacitor includes: an operational amplifier, connected in a negative feedback configuration; a first compensation transistor; a second compensation transistor; and a compensation capacitor. The compensation capacitor is chosen so that the ratio of the area of the compensation capacitor divided by the area of the first capacitor is an area ratio “AR”. The operational amplifier sets the gate voltage of the compensation capacitor to be the same as the gate voltage of the first capacitor. The ratio of the size of the second compensation transistor divided by the size of the second compensation transistor is also the area ration “AR”. Consequently, the first compensation transistor and the second compensation transistor drain current out of the compensation capacitor and first capacitor, respectively, approximately equal to the amount tunneling leakage current through the compensation capacitor and first capacitor, respectively.

摘要翻译： 一种用于补偿穿过第一电容器的隧穿泄漏电流的方法和装置包括：以负反馈配置连接的运算放大器; 第一补偿晶体管; 第二补偿晶体管; 和补偿电容器。 选择补偿电容器，使得补偿电容器的面积除以第一电容器的面积的比率是面积比“AR”。 运算放大器将补偿电容器的栅极电压设置为与第一电容器的栅极电压相同。 第二补偿晶体管的尺寸除以第二补偿晶体管的尺寸的比率也是面积比“AR”。 因此，补偿电容器和第一电容器中的第一补偿晶体管和第二补偿晶体管漏极电流分别大约分别等于通过补偿电容器和第一电容器的隧穿泄漏电流的量。

公开(公告)号：US06242790B1

公开(公告)日：2001-06-05

申请号：US09385550

申请日：1999-08-30

申请人： Ting Y. Tsui ,  Reading Maley

发明人： Ting Y. Tsui ,  Reading Maley

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  G11C17/16 ,  G11C27/00 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a new polysilicon fuse structure for implementation within integrated circuit devices so as to permit programming of the same. The polysilicon fuse structure includes a first electrical contact region, a second electrical contact region, and multiple fuse regions interconnected between the first electrical contact region and the second electrical contact region. The multiple fuse regions are formed of a plurality of strips, each being of a different width and/or length, which are disposed in a spaced-apart relationship so as to form a small opening between adjacent strips. A number of the plurality of strips is selectively blown when a predetermined amount of current is passed from one of the first and second electrical contact regions through the plurality of strips to the other one of the first and second electrical contact regions so to limit the current passing to an integrated circuit device connected thereto during normal operating conditions.

摘要翻译： 提供了一种用于在集成电路器件内实现的新的多晶硅熔丝结构，以便允许对其进行编程。 多晶硅熔丝结构包括第一电接触区域，第二电接触区域和在第一电接触区域和第二电接触区域之间互连的多个熔断器区域。 多个保险丝区域由多个条带形成，每个条带具有不同的宽度和/或长度，它们以间隔开的关系设置，以便在相邻条带之间形成小的开口。 当预定量的电流从第一和第二电接触区域中的一个通过多个条带到第一和第二电接触区域中的另一个时，选择性地吹制多个条带中的多个，以限制电流 在正常操作条件下传递到与其连接的集成电路装置。

公开(公告)号：US6081152A

公开(公告)日：2000-06-27

申请号：US165489

申请日：1998-10-02

申请人： Reading Maley

发明人： Reading Maley

IPC分类号： H03K5/08 ,  H03K19/003

CPC分类号： H03K19/00315 ,  H03K5/08

摘要： An output buffer interfaces a digital system having devices designed for low operating voltages to an output coupled to an external system having higher operating voltages. The output buffer drives the output to one of a high output voltage and a low output voltage while limiting voltage across terminals of devices within the output buffer. The output buffer includes a pull-up stack of a first plurality of devices, coupled between a high power supply and the output, which turn on when the output is driven to the high output voltage and which turn off when the output is driven to the low output voltage. The voltage difference between the output and the high power supply is distributed across the first plurality of devices when the output is driven to the low output voltage. The output buffer further includes a pull-down stack of a second plurality of devices, coupled between a low power supply and the output, which turn on when the output is driven to the low output voltage and which turn off when the output is driven to the high output voltage. The voltage difference between the output and the low power supply is distributed across the second plurality of devices when the output is driven to the high output voltage. The output buffer further includes a clamping circuit, coupled to the output and to a predetermined node of the first and second plurality of devices, for limiting voltage across terminals of each of the first and second plurality of devices by discharging down the predetermined node when the output is driven to the low output voltage and by charging up the predetermined node when the output is driven to the high output voltage.

摘要翻译： 输出缓冲器将具有设计用于低工作电压的设备的数字系统与耦合到具有较高工作电压的外部系统的输出相连接。 输出缓冲器将输出驱动为高输出电压和低输出电压之一，同时限制输出缓冲器内的器件端子间的电压。 输出缓冲器包括耦合在高电源和输出之间的第一多个器件的上拉电阻，当输出被驱动到高输出电压时，该上拉电路导通，并且当输出被驱动到 低输出电压。 当输出被驱动到低输出电压时，输出和高电源之间的电压差分布在第一多个器件上。 输出缓冲器还包括耦合在低功率电源和输出之间的第二多个器件的下拉堆叠，当输出被驱动到低输出电压时，输出被接通，当输出被驱动到 高输出电压。 当输出被驱动到高输出电压时，输出和低电源之间的电压差分布在第二多个器件上。 所述输出缓冲器还包括钳位电路，其耦合到所述第一和第二多个器件的输出端和预定节点，用于通过在所述第一和第二多个器件中的所述第一和第二多个器件中的每一个的端子 输出被驱动到低输出电压，并且当输出被驱动到高输出电压时通过给预定节点充电。

公开(公告)号：US08598958B1

公开(公告)日：2013-12-03

申请号：US13406772

申请日：2012-02-28

申请人： Reading Maley

发明人： Reading Maley

IPC分类号： H03K3/03

CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03L1/02 ,  H03L7/0995

摘要： An apparatus comprising a transconductance control circuit, a boost control circuit, a current computation circuit and an oscillator circuit. The transconductance control circuit may be configured to generate a current control signal in response to (i) a voltage control signal and (ii) a plurality of range control signals. The boost control circuit may be configured to generate a current boost signal in response to a reference current signal and an enable signal. The current computation circuit may be configured to generate a first control signal and a second control signal in response to the current boost signal and the current control signal. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to the first control signal and the second control signal.

摘要翻译： 一种包括跨导控制电路，升压控制电路，电流计算电路和振荡器电路的装置。 跨导控制电路可以被配置为响应于（i）电压控制信号和（ii）多个范围控制信号而产生电流控制信号。 升压控制电路可以被配置为响应于参考电流信号和使能信号而产生电流升压信号。 当前计算电路可以被配置为响应于当前升压信号和电流控制信号而产生第一控制信号和第二控制信号。 振荡器电路可以被配置为响应于第一控制信号和第二控制信号而产生以特定频率振荡的输出信号。

公开(公告)号：US08138847B1

公开(公告)日：2012-03-20

申请号：US12861133

申请日：2010-08-23

申请人： Reading Maley

发明人： Reading Maley

IPC分类号： H03B5/24 ,  H03K3/03 ,  H03L1/00 ,  H03L1/02

CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03L1/02 ,  H03L7/0995

摘要： An apparatus comprising a transconductance control circuit, a boost control circuit, a current computation circuit and an oscillator circuit. The transconductance control circuit may be configured to generate a current control signal in response to (i) a voltage control signal and (ii) a plurality of range control signals. The boost control circuit may be configured to generate a current boost signal in response to a reference current signal and an enable signal. The current computation circuit may be configured to generate a first control signal and a second control signal in response to the current boost signal and the current control signal. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to the first control signal and the second control signal.

摘要翻译： 一种包括跨导控制电路，升压控制电路，电流计算电路和振荡器电路的装置。 跨导控制电路可以被配置为响应于（i）电压控制信号和（ii）多个范围控制信号而产生电流控制信号。 升压控制电路可以被配置为响应于参考电流信号和使能信号而产生电流升压信号。 当前计算电路可以被配置为响应于当前升压信号和电流控制信号而产生第一控制信号和第二控制信号。 振荡器电路可以被配置为响应于第一控制信号和第二控制信号而产生以特定频率振荡的输出信号。

公开(公告)号：US6054888A

公开(公告)日：2000-04-25

申请号：US165911

申请日：1998-10-02

申请人： Reading Maley

发明人： Reading Maley

IPC分类号： H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： A level shifter interfaces a digital system having devices designed for low operating voltages to an external system having higher operating voltages. The level shifter is comprised of two level shifting stages. Each level shifting stage includes a pull-up stack of a plurality of pull-up devices, coupled between a high power supply and a coupling node, which turn on when the coupling node is driven to a high shifted voltage, which is substantially the voltage at the high power supply, and which turn off when the coupling node is driven to a low shifted voltage, which is substantially the voltage at a low power supply. Each level shifting stage further includes a pull-down stack of a plurality of pull-down devices, coupled between the low power supply and the coupling node, which turn on when the coupling node is driven to the low shifted voltage and which turn off when the coupling node is driven to the high shifted voltage. Each level shifting stage further includes a clamping circuit, coupled to the coupling node and to a predetermined node of the plurality of pull-up and pull-down devices, for limiting voltage across terminals of each of the plurality of pull-up and pull-down devices by discharging down the predetermined node when the coupling node is driven to the low shifted voltage and by charging up the predetermined node when the coupling node is driven to the high shifted voltage. Thus, the level shifter shifts a lower core voltage range from the digital system to a higher shifted voltage range of the external system while limiting voltage across terminals of devices within the level shifter to prevent device breakdown and degradation.

摘要翻译： 电平转换器将具有用于低工作电压的设备的数字系统与具有较高工作电压的外部系统接口。 电平移位器由两个电平转换级组成。 每个电平移位级包括耦合在高电源和耦合节点之间的多个上拉器件的上拉堆叠，当耦合节点被驱动到高移位电压时，该高电压和耦合节点接通，其基本上是电压 在高电源下，并且当耦合节点被驱动到低电平的电压时，其关闭，其基本上是低电源处的电压。 每个电平转换级还包括耦合在低功率电源和耦合节点之间的多个下拉装置的下拉堆叠，当耦合节点被驱动到低电平移位电压时，该下拉组件接通， 耦合节点被驱动到高位移电压。 每个电平移位级还包括钳位电路，其耦合到所述耦合节点并连接到所述多个上拉和下拉器件中的预定节点，用于限制所述多个上拉和下拉器件中的每一个的端子两端的电压。 当耦合节点被驱动到低位移电压时通过向下放大预定节点并且当耦合节点被驱动到高移位电压时对预定节点充电。 因此，电平移位器将较低的核心电压范围从数字系统转移到外部系统的较高移位电压范围，同时限制电平移位器内的器件的端子两端的电压，以防止器件击穿和退化。