公开(公告)号：US12046543B2

公开(公告)日：2024-07-23

申请号：US17679862

申请日：2022-02-24

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Han-Chieh Hsieh ,  Chao-Min Lai ,  Cheng-Chen Huang ,  Nan-Chin Chuang

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.

公开(公告)号：US11579643B2

公开(公告)日：2023-02-14

申请号：US17088560

申请日：2020-11-03

Applicant: Realtek Semiconductor Corp.

Inventor： Chao-Min Lai ,  Hung-Wei Wang ,  Tang-Hung Chang ,  Han-Chieh Hsieh ,  Chun-Yi Kuo

IPC: G05F1/46 ,  G06F1/3296 ,  H02M3/156

Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

公开(公告)号：US20220416789A1

公开(公告)日：2022-12-29

申请号：US17695821

申请日：2022-03-15

Applicant: Realtek Semiconductor Corp.

Inventor： Chao-Min Lai ,  Han-Chieh Hsieh ,  Tang-Hung Chang ,  Hung-Wei Wang ,  Chun-Yi Kuo

IPC: H03K19/0185 ,  H03K19/17784 ,  H03K19/00

Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

公开(公告)号：US20210191723A1

公开(公告)日：2021-06-24

申请号：US17123723

申请日：2020-12-16

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Han-Chieh Hsieh

IPC: G06F9/30 ,  G06N3/08

Abstract: A chip is capable of executing an exception handling method. The chip includes a processor. The processor includes a control circuit, a voltage detection circuit, a neural network circuit, and a processing circuit. The control circuit is configured to read and execute an instruction. The voltage detection circuit is configured to detect a voltage of the processor to output a voltage value. The neural network circuit outputs an output signal according to the voltage value and the instruction. The processing circuit executes an exception process when the output signal is abnormal. Therefore, the chip can predict whether the processor may operate at a voltage less than a rated voltage and take a corresponding measure, to ensure normal operation of the chip.

公开(公告)号：US20210141407A1

公开(公告)日：2021-05-13

申请号：US17088560

申请日：2020-11-03

Applicant: Realtek Semiconductor Corp.

Inventor： Chao-Min Lai ,  Hung-Wei Wang ,  Tang-Hung Chang ,  Han-Chieh Hsieh ,  Chun-Yi Kuo

IPC: G05F1/46 ,  G06F1/3296 ,  H02M3/156

Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

公开(公告)号：US11646738B2

公开(公告)日：2023-05-09

申请号：US17695821

申请日：2022-03-15

Applicant: Realtek Semiconductor Corp.

Inventor： Chao-Min Lai ,  Han-Chieh Hsieh ,  Tang-Hung Chang ,  Hung-Wei Wang ,  Chun-Yi Kuo

IPC: H03K19/0185 ,  H03K19/00 ,  H03K19/17784

CPC classification number: H03K19/01855 ,  H03K19/0016 ,  H03K19/17784

Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

公开(公告)号：US11227851B2

公开(公告)日：2022-01-18

申请号：US16718256

申请日：2019-12-18

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Chao-Min Lai ,  Ping-Chia Wang ,  Han-Chieh Hsieh ,  Tang-Hung Chang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

Abstract: A control device and a circuit board are provided. The control device can cooperate with the circuit board, and includes a ball grid array. The ball grid array includes a plurality of power balls and a plurality of ground balls, which are jointly arranged in a ball region. The power balls and the ground balls are respectively divided into a plurality of power ball groups and a plurality of ground ball groups. One of the ground ball groups includes two ground balls and is adjacent to a power ball group. A ball pitch between the two ground balls is greater than that between one of the power balls and one of the ground balls adjacent to each other. The circuit board includes a contact pad array corresponding to the ball grid array of the control device so that the control device can be disposed on the circuit board.