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公开(公告)号：US11475288B2
公开(公告)日：2022-10-18
申请号：US16674488
申请日：2019-11-05
摘要： Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.
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公开(公告)号：US10063255B2
公开(公告)日：2018-08-28
申请号：US15618530
申请日：2017-06-09
发明人： Marcus Riedel , Devon Jenson
摘要： In some examples, a device includes an integrated circuit comprising a computational unit configured to process at least two input bit streams that each include a sequential set of data bits or two or more sets of data bits in parallel that is deterministically encoded to represent numerical values based on a probability that any data bit in the bit stream is high. In some examples, the computational unit includes a convolver configured to generate pair-wise bit combinations of the data bits of the input bit streams. In some examples, e computational unit further includes a stochastic computational unit configured to perform a computational operation on the pair-wise bit combinations and produce an output bit stream having a set of data bits indicating a result of the computational operation based on a probability that any data bit in the set of data bits of the output bit stream is high.
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公开(公告)号：US20170255225A1
公开(公告)日：2017-09-07
申请号：US15448997
申请日：2017-03-03
摘要： In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.
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公开(公告)号：US10520975B2
公开(公告)日：2019-12-31
申请号：US15448997
申请日：2017-03-03
摘要： In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.
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公开(公告)号：US20190121839A1
公开(公告)日：2019-04-25
申请号：US16165713
申请日：2018-10-19
发明人： Soheil Mohajer , Zhiheng Wang , Kiarash Bazargan , Marcus Riedel , David J. Lilja , Sayed Abdolrasoul Faraji
IPC分类号： G06F17/18
摘要： In some examples, a device includes shuffling circuitry configured to receive an input unary bit stream and generate a shuffled bit stream by selecting n-tuple combinations of bits of the input unary bit stream. The device also includes stochastic logic circuitry having a plurality of stochastic computational units configured to perform operations on the shuffled bit stream in parallel to produce an output unary bit stream, each of the stochastic computational units operating on a different one of the n-tuple combinations of the bits.
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公开(公告)号：US11018689B2
公开(公告)日：2021-05-25
申请号：US16165713
申请日：2018-10-19
发明人： Soheil Mohajer , Zhiheng Wang , Kiarash Bazargan , Marcus Riedel , David J. Lilja , Sayed Abdolrasoul Faraji
摘要： In some examples, a device includes shuffling circuitry configured to receive an input unary bit stream and generate a shuffled bit stream by selecting n-tuple combinations of bits of the input unary bit stream. The device also includes stochastic logic circuitry having a plurality of stochastic computational units configured to perform operations on the shuffled bit stream in parallel to produce an output unary bit stream, each of the stochastic computational units operating on a different one of the n-tuple combinations of the bits.
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公开(公告)号：US20170359082A1
公开(公告)日：2017-12-14
申请号：US15618530
申请日：2017-06-09
发明人： Marcus Riedel , Devon Jenson
摘要： In some examples, a device includes an integrated circuit comprising a computational unit configured to process at least two input bit streams that each include a sequential set of data bits or two or more sets of data bits in parallel that is deterministically encoded to represent numerical values based on a probability that any data bit in the bit stream is high. In some examples, the computational unit includes a convolver configured to generate pair-wise bit combinations of the data bits of the input bit streams. In some examples, e computational unit further includes a stochastic computational unit configured to perform a computational operation on the pair-wise bit combinations and produce an output bit stream having a set of data bits indicating a result of the computational operation based on a probability that any data bit in the set of data bits of the output bit stream is high.
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公开(公告)号：US11275563B2
公开(公告)日：2022-03-15
申请号：US16906122
申请日：2020-06-19
发明人： Mohammadhassan Najafi , David J. Lilja , Marcus Riedel , Kiarash Bazargan , Sayed Abdolrasoul Faraji , Bingzhe Li
摘要： Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.
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公开(公告)号：US10740686B2
公开(公告)日：2020-08-11
申请号：US15869453
申请日：2018-01-12
发明人： Mohammadhassan Najafi , Shiva Jamalizavareh , David J. Lilja , Marcus Riedel , Kiarash Bazargan , Ramesh Harjani
摘要： Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.
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公开(公告)号：US20180204131A1
公开(公告)日：2018-07-19
申请号：US15869453
申请日：2018-01-12
发明人： Mohammadhassan Najafi , Shiva Jamalizavareh , David J. Lilja , Marcus Riedel , Kiarash Bazargan , Ramesh Harjani
CPC分类号： G06N7/005 , G06F7/582 , G06J1/00 , G06N3/0472 , H03K7/08
摘要： Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.
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