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8 条记录 (耗时 0.018 秒)

    Tri-state output buffer circuit
    1.
    发明授权
    Tri-state output buffer circuit 失效
    三态输出缓冲电路

    公开(公告)号：US5548229A

    公开(公告)日：1996-08-20

    申请号：US364105

    申请日：1994-12-27

    申请人： Reiji Segawa ,  Tatsuhiko Nagahisa

    发明人： Reiji Segawa ,  Tatsuhiko Nagahisa

    IPC分类号： H03K19/094 ,  H03K19/0948

    CPC分类号： H03K19/09429

    摘要： A single data output terminal and an output portion having a pair of output control terminals for generating a ternary output, are disposed for a plurality of data input terminals and a plurality of control input terminals in the same number as that of the data input terminals. Input changeover portions have (i) a state where data signals can be entered into the output control terminals and (ii) a state where the data signals cannot be entered into the output control terminals. An input control portion supplies, according to the states of control signals entered therein, a changeover signal for switching the input changeover portions to (i) a mode in which one of the input changeover portions is set to the conductive state, or (ii) a mode in which all of the input changeover portions are set to the non-conductive state. According to the states of entered control signals, an output control portion controls the output portion such that a high impedance signal is supplied according to a changeover signal for setting all of the input changeover portions to the non-conductive state, and that there is generated an output signal identical with the value of an entered binary data signal according to a changeover signal for setting one of the input changeover portions to the conductive state.

    摘要翻译： 对于多个数据输入端子和与数据输入端子的数量相同的多个控制输入端子，设置单个数据输出端子和具有用于产生三元输出的一对输出控制端子的输出部分。 输入切换部具有（i）能够将数据信号输入到输出控制端子的状态，以及（ii）数据信号不能输入到输出控制端子的状态。 输入控制部分根据其中输入的控制信号的状态，将输入切换部分切换为（i）将输入切换部分中的一个设置为导通状态的模式，或者（ii） 将所有输入切换部分设定为非导通状态的模式。 根据输入的控制信号的状态，输出控制部分控制输出部分，使得根据用于将所有输入切换部分设置为非导通状态的切换信号提供高阻抗信号，并且产生 与输入的二进制数据信号的值相符的输出信号，根据用于将输入转换部分之一设置为导通状态的转换信号。

    Apparatus for translation between virtual and physical addresses using a virtual page number, a physical page number, a process identifier and a global bit
    2.
    发明授权
    Apparatus for translation between virtual and physical addresses using a virtual page number, a physical page number, a process identifier and a global bit 有权
    用于使用虚拟页码，物理页号，进程标识符和全局位在虚拟和物理地址之间进行转换的装置

    公开(公告)号：US06564311B2

    公开(公告)日：2003-05-13

    申请号：US09487343

    申请日：2000-01-19

    申请人： Masahide Kakeda ,  Reiji Segawa

    发明人： Masahide Kakeda ,  Reiji Segawa

    IPC分类号： G06F1200

    CPC分类号： G06F12/1036 ,  G06F12/109 ,  G06F12/1483 ,  G06F2212/656

    摘要： An address translation apparatus comprises: entry storage means for storing a plurality of entries, each entry containing a virtual page number, a physical page number, and a process identifier which is composed of plural bits; comparison information storage means for storing comparison information which defines a method for comparing a process identifier possessed by a process that is currently executed, with the process identifier in each entry; process comparison means for comprising the process identifier possessed by the process that is currently executed, with the process identifier in the entry, on the basis of the comparison information; and entry retrieval means for retrieving, from the entry storage means, an entry including a virtual page number equal to a virtual page number supplied from the outside, and a process identifier which matches the process identifier of the currently executed process, according to the result of comparison by the process comparison means. Therefore, when a physical memory has a content which can be shared between at least two processes, effective utilization of memory area can be achieved by unifying entries with respect to these processes.

    摘要翻译： 地址转换装置包括：条目存储装置，用于存储多个条目，每个条目包含虚拟页码，物理页号和由多个比特组成的进程标识符; 比较信息存储装置，用于存储定义用于将当前执行的处理所拥有的进程标识符与每个条目中的进程标识符进行比较的方法的比较信息; 处理比较装置，用于根据比较信息，将当前执行的进程所拥有的进程标识符与条目中的进程标识符相结合; 以及条目检索装置，用于从条目存储装置检索包括等于从外部提供的虚拟页码的虚拟页码的条目以及与当前执行的处理的处理标识符相匹配的处理标识符，根据该结果 通过过程比较手段进行比较。 因此，当物理存储器具有能够在至少两个进程之间共享的内容时，可以通过统一关于这些处理的条目来实现存储区域的有效利用。

    Layout input apparatus, layout input method, layout verification apparatus, and layout verification method
    3.
    发明授权
    Layout input apparatus, layout input method, layout verification apparatus, and layout verification method 失效
    布局输入装置，布局输入法，布局验证装置和布局验证方法

    公开(公告)号：US06308143B1

    公开(公告)日：2001-10-23

    申请号：US08802643

    申请日：1997-02-19

    申请人： Reiji Segawa

    发明人： Reiji Segawa

    IPC分类号： G06F1750

    CPC分类号： G06F17/5081 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/00014

    摘要： A layout input apparatus of the present application includes: an input section for inputting first coordinate information representing a position of a first circuit portion included in a first semiconductor integrated circuit and second coordinate information representing a position of a second circuit portion included in a second semiconductor integrated circuit. The layout input apparatus further includes a control section for performing a predetermined coordinate transformation with respect to the second coordinate information; and a storage section for storing the first coordinate information as at least a part of first layout data representing a layout of the first semiconductor integrated circuit and storing the transformed second coordinate information as at least a part of second layout data representing a layout of the second semiconductor integrated circuit.

    摘要翻译： 本申请的布局输入装置包括：输入部分，用于输入表示第一半导体集成电路中包括的第一电路部分的位置的第一坐标信息和表示包括在第二半导体中的第二电路部分的位置的第二坐标信息 集成电路。 布局输入装置还包括：控制部分，用于对第二坐标信息执行预定的坐标变换; 以及存储部分，用于存储作为表示第一半导体集成电路的布局的第一布局数据的至少一部分的第一坐标信息，并且存储变换的第二坐标信息作为表示第二坐标信息的布局的第二布局数据的至少一部分 半导体集成电路。

    Output circuit and data transfer device employing the same
    5.
    发明授权
    Output circuit and data transfer device employing the same 失效
    输出电路和数据传输装置

    公开(公告)号：US5239214A

    公开(公告)日：1993-08-24

    申请号：US750119

    申请日：1991-08-26

    申请人： Reiji Segawa ,  Ichiro Okabayashi

    发明人： Reiji Segawa ,  Ichiro Okabayashi

    IPC分类号： H03K19/094

    CPC分类号： H03K19/09429

    摘要： An output circuit for a data transfer device includes first and second control inputs, a data input and a data output. The first control input controls whether the data output is generated in accordance with an ordinary type or an open drain type circuit operation, while the second control input controls whether the data output generated in accordance with the ordinary type circuit operation is set to an active state or an inactive state.

    摘要翻译： 用于数据传输装置的输出电路包括第一和第二控制输入，数据输入和数据输出。 第一控制输入根据普通类型或开漏型电路操作来控制数据输出是否产生，而第二控制输入控制根据普通型电路操作生成的数据输出是否被设置为活动状态 或非活动状态。

    Data processing device and method
    6.
    发明授权
    Data processing device and method 有权
    数据处理装置及方法

    公开(公告)号：US06598147B1

    公开(公告)日：2003-07-22

    申请号：US09674409

    申请日：2001-02-28

    申请人： Reiji Segawa

    发明人： Reiji Segawa

    IPC分类号： G06F1210

    CPC分类号： G06F12/1027

    摘要： The present invention has for its object to provide a data processing apparatus which improves the point that in data processing employing an associative storage device, performing the high speed processing has been impossible in the full-associative constitution since each way (entry) is subjected to the sequential processing respectively in search processing. The data processing apparatus includes a TLB comprising an information pair specifying information means (RP), a first information holding means (PTE-Hi), and a second information holding means (PTE-Lo). The high speed processing against information held in a TLB memory section is realized by performing the search processing employing information held in the above-mentioned means.

    摘要翻译： 本发明的目的是提供一种数据处理装置，其改进了在使用关联存储装置的数据处理中执行高速处理的点，因为在每个方式（条目）被执行时，完全关联的结构是不可能的 顺序处理分别在搜索处理中。 该数据处理装置包括一个包括信息对指定信息装置（RP），第一信息保持装置（PTE-Hi）和第二信息保持装置（PTE-Lo））的TLB。 通过使用以上述方式保存的信息进行搜索处理，来实现针对TLB存储器部分中保存的信息的高速处理。