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公开(公告)号：US08093689B2
公开(公告)日：2012-01-10
申请号：US11772272
申请日：2007-07-02
IPC分类号： H01L23/58
CPC分类号： H01L23/60 , H01L2223/6677 , H01L2924/0002 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating portion is electrically isolates the semiconductor sensor device from the first conductive contact region and second conductive contact region.
摘要翻译： 半导体传感器装置电耦合到物体。 附接构件将半导体传感器装置附接到物体。 附接构件包括第一导电接触区域和第二导电接触区域。 绝缘部分将半导体传感器装置与第一导电接触区域和第二导电接触区域电隔离。
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2.发明授权公开(公告)号：US07863920B2
公开(公告)日：2011-01-04
申请号：US11854275
申请日：2007-09-12
IPC分类号： G01R31/26
CPC分类号： G01R31/002
摘要： A method of conducting an electrostatic discharge test on an integrated circuit is described. The method comprises configuring a test board assembly to emulate characteristics of a system in which the integrated circuit is to be used, coupling the integrated circuit to the test board assembly, and applying an electrostatic discharge test signal of system-level type to the test board assembly.
摘要翻译： 对集成电路进行静电放电试验的方法进行说明。 该方法包括配置测试板组件以仿真其中使用集成电路的系统的特性，将集成电路耦合到测试板组件，以及将系统级类型的静电放电测试信号施加到测试板 部件。
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3.发明申请公开(公告)号：US20090066354A1
公开(公告)日：2009-03-12
申请号：US11854275
申请日：2007-09-12
IPC分类号： G01R31/02
CPC分类号： G01R31/002
摘要： A method of conducting an electrostatic discharge test on an integrated circuit is described. The method comprises configuring a test board assembly to emulate characteristics of a system in which the integrated circuit is to be used, coupling the integrated circuit to the test board assembly, and applying an electrostatic discharge test signal of system-level type to the test board assembly.
摘要翻译： 对集成电路进行静电放电试验的方法进行说明。 该方法包括配置测试板组件以仿真其中使用集成电路的系统的特性，将集成电路耦合到测试板组件，以及将系统级类型的静电放电测试信号施加到测试板 部件。
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公开(公告)号：US20090012439A1
公开(公告)日：2009-01-08
申请号：US11772272
申请日：2007-07-02
CPC分类号： H01L23/60 , H01L2223/6677 , H01L2924/0002 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating portion is electrically isolates the semiconductor sensor device from the first conductive contact region and second conductive contact region.
摘要翻译： 半导体传感器装置电耦合到物体。 附接构件将半导体传感器装置附接到物体。 附接构件包括第一导电接触区域和第二导电接触区域。 绝缘部分将半导体传感器装置与第一导电接触区域和第二导电接触区域电隔离。
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公开(公告)号：US07694247B2
公开(公告)日：2010-04-06
申请号：US10569986
申请日：2005-03-17
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A program-controlled arrangement for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit comprises a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards. A simulator device is connected downstream of the pre-processor which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator. An analysis device is connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.
摘要翻译： 用于在设计中或集成电路的概念中识别ESD和/或闭锁弱点的程序控制布置包括预处理器，其处理关于集成电路的描述的第一数据，关于 集成电路已经具有ESD特征的电路部件，以及包含有关ESD测试标准信息的第三个数据。 模拟器装置连接在预处理器的下游，其具有模拟器，通过使用由预处理器生成的第四和第五数据执行集成电路的ESD模拟，其具有用于控制ESD模拟的监视控制器 序列在模拟器中。 分析装置连接在模拟器装置的下游，对其模拟装置的物理有效性和有意义性进行评估，并对具有物理上相关的ESD故障事件的模拟运行进行标记。
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6.发明申请公开(公告)号：US20060056121A1
公开(公告)日：2006-03-16
申请号：US10536176
申请日：2003-11-24
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply voltage. When electrostatic discharges or electrical over-stress occurs, current flows through the conductive path formed through the first and second protective elements. A current path that contains a circuit element limits current through the first protective element is connected in parallel with the first protective element. The first protective element has blocking behavior when no electrostatic discharges or electrical over-stress occurs, a limited current flows through the current path and the second protective element.
摘要翻译： 描述了保护集成电路免受静电放电或电过压的电路。 电路装置具有在集成电路的连接和电源电压之间串联连接的第一和第二保护元件。 当发生静电放电或电过压时，电流流过形成在第一和第二保护元件上的导电路径。 包含电路元件的电流路径限制通过第一保护元件的电流与第一保护元件并联连接。 当不产生静电放电或电过度应力时，第一保护元件具有阻塞行为，有限的电流流过电流通路和第二保护元件。
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7.发明申请公开(公告)号：US20050003564A1
公开(公告)日：2005-01-06
申请号：US10866863
申请日：2004-06-14
申请人： Silke Bargstadt-Franke , Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Silke Bargstadt-Franke , Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H01L23/544 , H01L23/60 , G01R31/26
CPC分类号： H01L22/34 , H01L23/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.
摘要翻译： 用于确定集成电路的ESD /闭锁强度的方法包括使用相同的制造工艺制造集成电路和测试结构。 测量测试结构的电气参数，并且从测量的参数值导出与集成电路相关联的特征值，其中特征值表征与集成电路相关联的ESD或闭锁特性曲线。 该方法还包括测试每种情况下的特征值是否在分配给它们的预定范围内，其中选择范围使得如果每种情况下的特征值在其范围内，则存在期望的ESD /闩锁强度。
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公开(公告)号：US06905892B2
公开(公告)日：2005-06-14
申请号：US10200067
申请日：2002-07-19
申请人： Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H01L27/04 , H01L21/822 , H01L23/60 , H01L29/74 , G01R31/26
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).
摘要翻译： 本发明创造了具有基板的半导体部件的操作方法; 具有施加到衬底的导电多晶硅条; 具有连接到导电多晶硅条的第一和第二电接触，使得它们之间形成电阻; 半导体部件在其具有第一差分电阻（Rdiff 1）的电流/电压范围内可逆地操作，直到对应于上限电压限制值（Vt）的电流限制值（It），并且在当前值更大 具有小于第一差分电阻（Rdiff 1）的第二差分电阻（Rdiff 2）。
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9.发明授权公开(公告)号：US07359169B2
公开(公告)日：2008-04-15
申请号：US10536176
申请日：2003-11-24
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H02H9/00 , H02H9/08 , H02H3/20 , H02H9/04 , H02H3/22 , H02H1/00 , H02H1/04 , H02H9/06 , H01C7/12
CPC分类号： H02H9/046
摘要： A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply voltage. When electrostatic discharges or electrical over-stress occurs, current flows through the conductive path formed through the first and second protective elements. A current path that contains a circuit element limits current through the first protective element is connected in parallel with the first protective element. The first protective element has blocking behavior when no electrostatic discharges or electrical over-stress occurs, a limited current flows through the current path and the second protective element.
摘要翻译： 描述了保护集成电路免受静电放电或电过压的电路。 电路装置具有在集成电路的连接和电源电压之间串联连接的第一和第二保护元件。 当发生静电放电或电过压时，电流流过形成在第一和第二保护元件上的导电路径。 包含电路元件的电流路径限制通过第一保护元件的电流与第一保护元件并联连接。 当不产生静电放电或电过度应力时，第一保护元件具有阻塞行为，有限的电流流过电流通路和第二保护元件。
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公开(公告)号：US06930501B2
公开(公告)日：2005-08-16
申请号：US10866863
申请日：2004-06-14
申请人： Silke Bargstädt-Franke , Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Silke Bargstädt-Franke , Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H01L23/544 , H01L23/60 , G01R31/26
CPC分类号： H01L22/34 , H01L23/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.
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