公开(公告)号：US07009404B2

公开(公告)日：2006-03-07

申请号：US10160740

申请日：2002-05-31

申请人： Martin Wendel ,  Richard Owen ,  Harald Gossner ,  Wolfgang Stadler ,  Philipp Riess ,  Martin Streibl ,  Kai Esmark

发明人： Martin Wendel ,  Richard Owen ,  Harald Gossner ,  Wolfgang Stadler ,  Philipp Riess ,  Martin Streibl ,  Kai Esmark

IPC分类号： G01R31/08 ,  G01R27/08

CPC分类号： G01R31/002 ,  G01R31/129

摘要： To test the ESD resistance of a semiconductor component, for example of a NOS transistor, which can be used as a PSD protective element in a chip, a direct current characteristic of the semiconductor component is monitored and the ESD resistance of the respective semiconductor component is inferred depending on this. In particular, the direct current failure threshold of the semiconductor component at which an increased leakage current occurs in the non-conducting direction of the semiconductor component can be monitored in operation of the semiconductor component using an applied direct current and the ESD resistance of the semiconductor component inferred depending on a change in this direct current failure threshold.

摘要翻译： 为了测试可用作芯片中的PSD保护元件的例如可用作PSD保护元件的NOS晶体管的半导体部件的ESD电阻，监视半导体部件的直流特性，并且各半导体部件的ESD电阻为 据此推断。 特别地，可以在使用所施加的直流电流和半导体的ESD电阻的半导体组件的操作中监视在半导体组件的非导通方向上发生增加的漏电流的半导体组件的直流故障阈值 根据该直流故障阈值的变化推断分量。

公开(公告)号：US06905892B2

公开(公告)日：2005-06-14

申请号：US10200067

申请日：2002-07-19

申请人： Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/74 ,  G01R31/26

CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).

摘要翻译： 本发明创造了具有基板的半导体部件的操作方法; 具有施加到衬底的导电多晶硅条; 具有连接到导电多晶硅条的第一和第二电接触，使得它们之间形成电阻; 半导体部件在其具有第一差分电阻（Rdiff 1）的电流/电压范围内可逆地操作，直到对应于上限电压限制值（Vt）的电流限制值（It），并且在当前值更大 具有小于第一差分电阻（Rdiff 1）的第二差分电阻（Rdiff 2）。

公开(公告)号：US20050003564A1

公开(公告)日：2005-01-06

申请号：US10866863

申请日：2004-06-14

申请人： Silke Bargstadt-Franke ,  Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Silke Bargstadt-Franke ,  Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H01L23/544 ,  H01L23/60 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

摘要翻译： 用于确定集成电路的ESD /闭锁强度的方法包括使用相同的制造工艺制造集成电路和测试结构。 测量测试结构的电气参数，并且从测量的参数值导出与集成电路相关联的特征值，其中特征值表征与集成电路相关联的ESD或闭锁特性曲线。 该方法还包括测试每种情况下的特征值是否在分配给它们的预定范围内，其中选择范围使得如果每种情况下的特征值在其范围内，则存在期望的ESD /闩锁强度。

公开(公告)号：US06930501B2

公开(公告)日：2005-08-16

申请号：US10866863

申请日：2004-06-14

申请人： Silke Bargstädt-Franke ,  Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Silke Bargstädt-Franke ,  Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H01L23/544 ,  H01L23/60 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

公开(公告)号：US20050263817A1

公开(公告)日：2005-12-01

申请号：US11138918

申请日：2005-05-26

申请人： Martin Wendel ,  Martin Streibl ,  Kai Esmark ,  Philipp Riess ,  Thomas Schafbauer

发明人： Martin Wendel ,  Martin Streibl ,  Kai Esmark ,  Philipp Riess ,  Thomas Schafbauer

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/78

摘要： A transistor contains a source region and a drain region. Two or more fill areas are formed such that the fill areas and the source and/or drain region engage in one another. The fill areas have vertical dimensions which are at least of equal size to the vertical dimensions of the source and/or of the drain region. The fill areas and the source and/or drain region extend at least partially over a common vertical section. The fill areas are formed from an oxide and/or a nitride.

摘要翻译： 晶体管包含源极区和漏极区。 形成两个或更多个填充区域，使得填充区域和源极和/或漏极区域彼此接合。 填充区具有与源极和/或漏极区域的垂直尺寸至少相等的垂直尺寸。 填充区域和源极和/或漏极区域至少部分地延伸在共同的垂直部分上。 填充区域由氧化物和/或氮化物形成。

公开(公告)号：US08710590B2

公开(公告)日：2014-04-29

申请号：US11454996

申请日：2006-06-16

申请人： Philipp Riess ,  Henning Feick ,  Martin Wendel

发明人： Philipp Riess ,  Henning Feick ,  Martin Wendel

IPC分类号： H01L23/62

CPC分类号： H01L29/1083 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/6659 ,  H01L29/78

摘要： In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.

摘要翻译： 在制造电子元件的方法中，通过引入掺杂原子来掺杂衬底。 在掺杂衬底中，通过掺杂掺杂原子形成电子部件的至少一个连接区域。 此外，通过掺杂掺杂原子至少在至少一个连接区域的下方形成至少一个附加的掺杂区域。 此外，通过以这样的方式掺杂掺杂原子在衬底中形成至少一个阱区，使得阱区掺杂至少在至少一个附加掺杂区下方被阻挡。

公开(公告)号：US20070010077A1

公开(公告)日：2007-01-11

申请号：US11454996

申请日：2006-06-16

申请人： Philipp Riess ,  Henning Feick ,  Martin Wendel

发明人： Philipp Riess ,  Henning Feick ,  Martin Wendel

IPC分类号： H01L21/22

CPC分类号： H01L29/1083 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/6659 ,  H01L29/78

摘要： In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.

摘要翻译： 在制造电子元件的方法中，通过引入掺杂原子来掺杂衬底。 在掺杂衬底中，通过掺杂掺杂原子形成电子部件的至少一个连接区域。 此外，通过掺杂掺杂原子至少在至少一个连接区域的下方形成至少一个附加的掺杂区域。 此外，通过以这样的方式掺杂掺杂原子在衬底中形成至少一个阱区，使得阱区掺杂至少在至少一个附加掺杂区下方被阻挡。

公开(公告)号：US08860225B2

公开(公告)日：2014-10-14

申请号：US13271878

申请日：2011-10-12

申请人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

发明人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L21/316 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

摘要翻译： 公开了在半导体部件上形成金属化层的结构和方法。 该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。 通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

公开(公告)号：US20130240884A1

公开(公告)日：2013-09-19

申请号：US13729145

申请日：2012-12-28

申请人： Hans-Joachim Barth ,  Horst Baumeister ,  Peter Baumgartner ,  Philipp Riess ,  Jesenka Veledar Krueger

发明人： Hans-Joachim Barth ,  Horst Baumeister ,  Peter Baumgartner ,  Philipp Riess ,  Jesenka Veledar Krueger

IPC分类号： H01L23/544 ,  H01L27/04

CPC分类号： H01L23/544 ,  H01L23/562 ,  H01L23/642 ,  H01L27/04 ,  H01L2224/16225

摘要： A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.

摘要翻译： 描述了可以可重复地测量微小电容及其变化的电容传感器和测量电路。 电容可以根据当地的环境条件（例如机械应力（例如翘曲或剪切应力）），机械压力，温度和/或湿度而变化。 可能需要提供集成到半导体芯片中的电容器，该电容器足够小并且敏感以准确地测量半导体芯片预期经历的条件。

公开(公告)号：US20120099243A1

公开(公告)日：2012-04-26

申请号：US13344714

申请日：2012-01-06

申请人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

IPC分类号： H01G4/005

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。