公开(公告)号：US08518811B2

公开(公告)日：2013-08-27

申请号：US13082793

申请日：2011-04-08

申请人： Philipp Riess ,  Domagoj Siprak

发明人： Philipp Riess ,  Domagoj Siprak

IPC分类号： H01L21/312

CPC分类号： H01L29/78 ,  H01L21/823437 ,  H01L23/48 ,  H01L27/0629 ,  H01L27/095 ,  H01L29/0692 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/872 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.

摘要翻译： 在一个实施例中，半导体器件包括设置在衬底的第一区域中的第一掺杂区域。 具有金属层的第一部分的第一金属电极设置在第一掺杂区域上并与第一掺杂区域接触。 第二掺杂区域设置在衬底的第二区域中。 电介质层设置在第二掺杂区上。 具有金属层的第二部分的第二金属电极设置在介电层上。 第二金属电极电容耦合到第二掺杂区域。

公开(公告)号：US20120256274A1

公开(公告)日：2012-10-11

申请号：US13082793

申请日：2011-04-08

申请人： Philipp Riess ,  Domagoj Siprak

发明人： Philipp Riess ,  Domagoj Siprak

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L23/48

CPC分类号： H01L29/78 ,  H01L21/823437 ,  H01L23/48 ,  H01L27/0629 ,  H01L27/095 ,  H01L29/0692 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/872 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the semiconductor device includes a first doped region disposed in a first region of a substrate. A first metal electrode having a first portion of a metal layer is disposed over and contacts the first doped region. A second doped region is disposed in a second region of the substrate. A dielectric layer is disposed on the second doped region. A second metal electrode having a second portion of the metal layer is disposed over the dielectric layer. The second metal electrode is capacitively coupled to the second doped region.

摘要翻译： 在一个实施例中，半导体器件包括设置在衬底的第一区域中的第一掺杂区域。 具有金属层的第一部分的第一金属电极设置在第一掺杂区域上并与第一掺杂区域接触。 第二掺杂区域设置在衬底的第二区域中。 电介质层设置在第二掺杂区上。 具有金属层的第二部分的第二金属电极设置在介电层上。 第二金属电极电容耦合到第二掺杂区域。

公开(公告)号：US08242579B2

公开(公告)日：2012-08-14

申请号：US12471435

申请日：2009-05-25

申请人： Philipp Riess

发明人： Philipp Riess

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.

摘要翻译： 一个或多个实施例涉及包括电容器的半导体芯片，所述电容器包括：多个导电板，每个所述板包括设置在所述第一导电条上或之下的第一导电条和第二导电条，所述第二导电 每个板的条带基本上平行于同一板的第一导电条，每个板的第二导电条通过至少一个导电通孔电耦合到板的第一导电条，每组的第二导电条 至少两个连续的板沿着板的长度方向彼此间隔开。

公开(公告)号：US08138539B2

公开(公告)日：2012-03-20

申请号：US11947591

申请日：2007-11-29

申请人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

IPC分类号： H01L27/108 ,  H01L21/20

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

公开(公告)号：US08062971B2

公开(公告)日：2011-11-22

申请号：US12051644

申请日：2008-03-19

申请人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

发明人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

摘要翻译： 公开了在半导体部件上形成金属化层的结构和方法。 该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。 通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

公开(公告)号：US07906831B2

公开(公告)日：2011-03-15

申请号：US12235614

申请日：2008-09-23

申请人： Peter Baumgartner ,  Philipp Riess

发明人： Peter Baumgartner ,  Philipp Riess

IPC分类号： H01L29/94

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/66 ,  H01L27/0207 ,  H01L27/08 ,  H01L28/10 ,  H01L2924/0002 ,  H03B1/02 ,  H01L2924/00

摘要： One or more embodiments relate to a semiconductor device, comprising: a inductor coil including a winding; and a capacitor arrangement including at least one capacitor, the capacitor arrangement electrically coupled to the inductor coil, the footprint of the capacitor arrangement at least partially overlapping the footprint of the inductor coil.

摘要翻译： 一个或多个实施例涉及半导体器件，包括：包括绕组的电感线圈; 以及电容器布置，其包括至少一个电容器，所述电容器布置电耦合到所述电感器线圈，所述电容器布置的所述覆盖区至少部分地与所述电感器线圈的覆盖区重叠。

公开(公告)号：US20070181924A1

公开(公告)日：2007-08-09

申请号：US11538227

申请日：2006-10-03

申请人： Peter Baumgartner ,  Philipp Riess ,  Thomas Benetik ,  Dieter Draxelmayr

发明人： Peter Baumgartner ,  Philipp Riess ,  Thomas Benetik ,  Dieter Draxelmayr

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes an integrated capacitor structure embodied at least partly in an electrically conductive plane and which is patterned such that a multiplicity of strip elements are present. A first group of strip elements constitutes a first electrode of the capacitor structure and a second group of strip elements constitutes a second electrode of the capacitor structure. The first strip elements together with the second strip elements being at least partly interlinked in one another, and at least one strip element may have a non-constant width along its length.

摘要翻译： 半导体部件包括至少部分地在导电平面中实现的集成电容器结构，并且被图案化以使得存在多个带​​状元件。 第一组带状元件构成电容器结构的第一电极，第二组带状元件构成电容器结构的第二电极。 第一带状元件与第二带状元件一起至少部分地彼此连接，并且至少一个带状元件沿其长度可以具有不恒定的宽度。

公开(公告)号：US06905892B2

公开(公告)日：2005-06-14

申请号：US10200067

申请日：2002-07-19

申请人： Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/74 ,  G01R31/26

CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).

摘要翻译： 本发明创造了具有基板的半导体部件的操作方法; 具有施加到衬底的导电多晶硅条; 具有连接到导电多晶硅条的第一和第二电接触，使得它们之间形成电阻; 半导体部件在其具有第一差分电阻（Rdiff 1）的电流/电压范围内可逆地操作，直到对应于上限电压限制值（Vt）的电流限制值（It），并且在当前值更大 具有小于第一差分电阻（Rdiff 1）的第二差分电阻（Rdiff 2）。

公开(公告)号：US08860225B2

公开(公告)日：2014-10-14

申请号：US13271878

申请日：2011-10-12

申请人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

发明人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L21/316 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

摘要翻译： 公开了在半导体部件上形成金属化层的结构和方法。 该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。 通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

公开(公告)号：US20130240884A1

公开(公告)日：2013-09-19

申请号：US13729145

申请日：2012-12-28

申请人： Hans-Joachim Barth ,  Horst Baumeister ,  Peter Baumgartner ,  Philipp Riess ,  Jesenka Veledar Krueger

发明人： Hans-Joachim Barth ,  Horst Baumeister ,  Peter Baumgartner ,  Philipp Riess ,  Jesenka Veledar Krueger

IPC分类号： H01L23/544 ,  H01L27/04

CPC分类号： H01L23/544 ,  H01L23/562 ,  H01L23/642 ,  H01L27/04 ,  H01L2224/16225

摘要： A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.

摘要翻译： 描述了可以可重复地测量微小电容及其变化的电容传感器和测量电路。 电容可以根据当地的环境条件（例如机械应力（例如翘曲或剪切应力）），机械压力，温度和/或湿度而变化。 可能需要提供集成到半导体芯片中的电容器，该电容器足够小并且敏感以准确地测量半导体芯片预期经历的条件。