公开(公告)号：US20150108541A1

公开(公告)日：2015-04-23

申请号：US14500324

申请日：2014-09-29

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Tetsuya NITTA

IPC: H01L29/739 ,  H01L29/10

CPC classification number: H01L29/7393 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/7395

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

Abstract translation: 可以抑制在整体电流能力下降的同时提高短路能力的半导体装置。 在半导体装置中，在半导体衬底的主表面上沿一个方向排列成一行的多个IGBT（绝缘栅双极型晶体管）包括位于一个方向上的末端的IGBT， IGBT位于极端。 位于极端的IGBT的电流能力高于位于中心位置的IGBT的电流能力。

公开(公告)号：US20150380532A1

公开(公告)日：2015-12-31

申请号：US14848412

申请日：2015-09-09

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Tetsuya NITTA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7393 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/41708

Abstract: In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.

公开(公告)号：US20170125558A1

公开(公告)日：2017-05-04

申请号：US15405725

申请日：2017-01-13

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Tetsuya NITTA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7393 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/7395

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

公开(公告)号：US20160064559A1

公开(公告)日：2016-03-03

申请号：US14835373

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Kouji TANAKA ,  Yasuki YOSHIHISA ,  Shunji KUBO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816

Abstract: A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n+ drain region toward an n+ source region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the n+ drain region toward the n+ source region.

Abstract translation: 半导体衬底具有主表面，其具有n型偏移区域，其具有由沿从n +漏极区域朝向n +源极区域的方向延伸的多个沟槽形成的沟槽部分。 多个沟槽中的导电层各自在从n +漏极区域向n +源极区域的方向上在主表面上延伸。