公开(公告)号：US20170125558A1

公开(公告)日：2017-05-04

申请号：US15405725

申请日：2017-01-13

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Tetsuya NITTA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7393 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/7395

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

公开(公告)号：US20150115410A1

公开(公告)日：2015-04-30

申请号：US14516806

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU ,  Takahiro MORI ,  Tetsuya NITTA

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

Abstract translation: 多个第一布线层布置在基板的主表面上，第一绝缘膜布置在多个第一布线层的上表面上，第二绝缘膜布置在第一绝缘膜的上表面上，并且 多个第二布线层布置在第二绝缘膜上。 金属电阻元件层布置在多个第二布线层中的至少一个第二布线层正下方。 多个导电层在垂直于主表面的Z方向上从多个第二布线层分别延伸到金属电阻元件层。 金属电阻元件层包括金属布线层。 多个导电层中的至少一个导电层的侧面的至少一部分连接到金属布线层。

公开(公告)号：US20150108541A1

公开(公告)日：2015-04-23

申请号：US14500324

申请日：2014-09-29

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Tetsuya NITTA

IPC: H01L29/739 ,  H01L29/10

CPC classification number: H01L29/7393 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/7395

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

Abstract translation: 可以抑制在整体电流能力下降的同时提高短路能力的半导体装置。 在半导体装置中，在半导体衬底的主表面上沿一个方向排列成一行的多个IGBT（绝缘栅双极型晶体管）包括位于一个方向上的末端的IGBT， IGBT位于极端。 位于极端的IGBT的电流能力高于位于中心位置的IGBT的电流能力。

公开(公告)号：US20130134549A1

公开(公告)日：2013-05-30

申请号：US13725389

申请日：2012-12-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuma ONISHI ,  Yoshitaka OTSU ,  Hiroshi KIMURA ,  Tetsuya NITTA ,  Shinichiro YANAGI ,  Katsumi MORII

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

Abstract translation: 一种半导体器件，其通过简单的工艺消除了对高填充性的需要及其制造方法。 在半导体衬底的表面上完成包括源极区和漏极区的高击穿电压横向MOS晶体管。 在半导体衬底的表面中制造在平面图中观察时围绕晶体管的沟槽。 在晶体管和沟槽中形成绝缘膜，以覆盖晶体管并在沟槽中形成气隙空间。 到达晶体管的源极区域和漏极区域的接触孔分别制成层间绝缘膜。

公开(公告)号：US20150380532A1

公开(公告)日：2015-12-31

申请号：US14848412

申请日：2015-09-09

Applicant: Renesas Electronics Corporation

Inventor： Mikio TSUJIUCHI ,  Tetsuya NITTA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7393 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/41708

Abstract: In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.

公开(公告)号：US20150214356A1

公开(公告)日：2015-07-30

申请号：US14605027

申请日：2015-01-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kosuke YOSHIDA ,  Tetsuya NITTA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L27/0922 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7809

Abstract: To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure, and a method of manufacturing the same.In the semiconductor device, an upper RESURF region is formed so as to contact with a first buried region on a side of the one main surface within a semiconductor substrate. The semiconductor substrate has a field oxide formed so as to reach the upper RESURF region on the one main surface. The semiconductor substrate includes a second conductivity type body region formed so as to contact with the upper RESURF region on a side of the one main surface and so as to neighbor the field oxide within the semiconductor substrate.

Abstract translation: 为了提供能够通过抑制双重RESURF结构的尺寸变化来抑制击穿电压降低的半导体器件及其制造方法。 在半导体器件中，上部RESURF区域形成为与半导体衬底内的一个主表面侧的第一掩埋区域接触。 半导体衬底具有形成为在一个主表面上到达上RESURF区域的场氧化物。 半导体衬底包括形成为与一个主表面侧上部RESURF区接触并与半导体衬底内的场氧化物相邻的第二导电类型体区。

公开(公告)号：US20170365553A1

公开(公告)日：2017-12-21

申请号：US15696395

申请日：2017-09-06

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU ,  Takahiro MORI ,  Tetsuya NITTA

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

公开(公告)号：US20150249126A1

公开(公告)日：2015-09-03

申请号：US14620401

申请日：2015-02-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hajime KATAOKA ,  Tatsuya SHIROMOTO ,  Tetsuya NITTA

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/761 ,  H01L21/764 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/522 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n+ type semiconductor region for source and an n+ type semiconductor region for drain separated from each other. The semiconductor substrate has, on the main surface thereof between the n+ type semiconductor region for source and the n+ type semiconductor region for drain, a gate electrode via an insulating film as a gate insulating film. The semiconductor substrate has, in the main surface thereof between the channel formation region below the gate electrode and the n+ type semiconductor region for drain, a LOCOS oxide film and an STI insulating. Of the LOCOS oxide film and the STI insulating film, the LOCOS oxide film is located on the side of the channel formation region and the STI insulating film is on the side of the n+ type semiconductor region DR for drain.

Abstract translation: 提供具有改进性能的半导体器件。 半导体衬底在其表层部分中具有用于源极的n +型半导体区域和用于漏极的n +型半导体区域彼此分离。 半导体衬底在其源极的n +型半导体区域和用于漏极的n +型半导体区域之间的主表面上具有作为栅极绝缘膜的绝缘膜的栅电极。 半导体衬底的主表面在栅电极下方的沟道形成区域和用于漏极的n +型半导体区域之间具有LOCOS氧化物膜和STI绝缘体。 在LOCOS氧化物膜和STI绝缘膜中，LOCOS氧化物膜位于沟道形成区域侧，STI绝缘膜位于用于漏极的n +型半导体区域DR侧。