公开(公告)号：US20230176883A1

公开(公告)日：2023-06-08

申请号：US17938475

申请日：2022-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi IGARASHI ,  Kenichi TAKEDA ,  Katsushige MATSUBARA ,  Tetsuya SHIBAYAMA

IPC: G06F9/455 ,  G06F9/4401

CPC classification number: G06F9/45541 ,  G06F9/4406

Abstract: According to one embodiment, a semiconductor device restricts an OS capable of using a functional block by an OS identifier written in an attribute register for restricting an accessible OS, and creates operation setting values of a first input unit, a second input unit, and a screen synthesis unit per OS to describe them in a setting value list stored in a shared memory, and each of the first input unit, second input unit, and screen synthesis unit has a mask circuit that refers to the OS identifier of the attribute register and in which write of the operation setting values into the setting register group of an own block is hampered, the operation setting values being described in the setting value list created by an OS other than the OS having a use authority for the own block.

公开(公告)号：US20240419605A1

公开(公告)日：2024-12-19

申请号：US18646506

申请日：2024-04-25

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi IGARASHI ,  Katsushige MATSUBARA ,  Kazuaki TERASHIMA

IPC: G06F12/1045 ,  G06F7/544 ,  G06F12/06

Abstract: A semiconductor device includes a scratchpad memory, a memory controller, and a MAC (multiply-accumulation) unit. The scratchpad memory is configured to store image data of N channels and includes M memories which are individually accessible, wherein M is integer of at least 2 and N is an integer of at least 2. The memory controller controls access to the scratchpad memory such that pixel data of the N channels which are arranged at a same position in image data of the N channels are respectively stored in difference memories in the M memories. The MAC unit includes a plurality of calculators to calculate pixel data of the N channels read from the scratchpad memory by using the memory controller and a weight parameter.

公开(公告)号：US20180276850A1

公开(公告)日：2018-09-27

申请号：US15861164

申请日：2018-01-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi IGARASHI ,  Seiji MOCHIZUKI ,  Katsushige MATSUBARA ,  Toshiyuki KAYA

IPC: G06T7/00 ,  G06T3/40 ,  G06T5/50 ,  G06T7/55

CPC classification number: G06T7/97 ,  G06T3/4092 ,  G06T5/50 ,  G06T7/55

Abstract: An image processing apparatus according to one embodiment determines target resolutions of a plurality of source images based on a first horizontal direction size and a first vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a first display, and a second horizontal direction size and a second vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a second display, and converts the resolution of each of a plurality of source images such that the resolution of each of a plurality of source images becomes the target resolution.