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公开(公告)号：US20170341646A1
公开(公告)日：2017-11-30
申请号：US15657559
申请日：2017-07-24
Applicant: Renesas Electronics Corporation
Inventor： Kazuaki TERASHIMA
IPC: B60W30/095 , B60W30/182 , B60W50/00
CPC classification number: B60W30/0956 , B60T2201/022 , B60W30/182 , B60W2050/0095 , B60W2540/22
Abstract: A semiconductor device includes an image recognition unit that outputs a recognition result based on image information received from a camera, and a determination unit that determines a control mode of a vehicle based on the recognition result and distance information received from a distance sensor.
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公开(公告)号：US20150367848A1
公开(公告)日：2015-12-24
申请号：US14711509
申请日：2015-05-13
Applicant: Renesas Electronics Corporation
Inventor： Kazuaki TERASHIMA
IPC: B60W30/095
CPC classification number: B60W30/0956 , B60T2201/022 , B60W30/182 , B60W2050/0095 , B60W2540/22
Abstract: To achieve an accurate transfer of control from a system to a driver, a semiconductor device includes: a recognition unit that recognizes an object present in the periphery of a vehicle based on a result of observation of the periphery of the vehicle; a route calculation unit that calculates, based on the recognized object, a travel route for the vehicle in an automatic control mode for automatically controlling the vehicle; and a mode control unit that transfers the vehicle from the automatic control mode to a manual control mode for controlling the vehicle according to an operation by a driver, when a travel route to avoid the recognized object cannot be calculated.
Abstract translation: 为了实现从系统到驾驶员的准确的控制传递，半导体装置包括：识别单元，其基于车辆周边的观察结果来识别车辆周围存在的物体; 路线计算单元，其基于所识别的对象，以自动控制车辆的自动控制模式来计算车辆的行驶路线; 以及模式控制单元，当不能计算避免识别对象的行驶路线时，将车辆从自动控制模式转移到用于根据驾驶员的操作来控制车辆的手动控制模式。
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公开(公告)号：US20240348939A1
公开(公告)日：2024-10-17
申请号：US18623841
申请日：2024-04-01
Applicant: Renesas Electronics Corporation
Inventor： Isao NAGAYOSHI , Kazuaki TERASHIMA
CPC classification number: H04N23/80 , H04N23/843
Abstract: A semiconductor device or image processing system includes n interface circuit and a channel composite circuit. The interface circuit outputs a first packet including the line data of the k-th line included in the image data of the first channel, and then outputs a second packet including the line data of the k-th line included in the image data of the second channel. The channel combination circuit writes, to the memory, the line data of the k-th line included in the image data of the first channel to the first address area, and then writes the line data of the k-th line included in the image data of the second channel to the second address area that is consecutive to the first address area.
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公开(公告)号：US20240054083A1
公开(公告)日：2024-02-15
申请号：US18336215
申请日：2023-06-16
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuaki TERASHIMA , Isao NAGAYOSHI , Atsushi NAKAMURA
CPC classification number: G06F13/1673 , G06F13/28 , G06F7/5443
Abstract: A semiconductor device capable of shortening processing time of a neural network is provided. The memory stores a compressed weight parameter. A plurality of multiply accumulators perform a multiply-accumulation operation to a plurality of pixel data and a plurality of weight parameters. A decompressor restores the compressed weight parameter stored in the memory to a plurality of weight parameters. A memory for weight parameter stores the plurality of weight parameters restored by the decompressor. The DMA controller transfers the plurality of weight parameters from the memory to the memory for weight parameter via the decompressor. A sequence controller writes down the plurality of weight parameters stored in the memory for weight parameter to a weight parameter buffer at write timing.
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公开(公告)号：US20150145997A1
公开(公告)日：2015-05-28
申请号：US14523871
申请日：2014-10-25
Applicant: Renesas Electronics Corporation
Inventor： Kazuaki TERASHIMA
CPC classification number: G06K9/00791 , B60R1/00 , B60R2300/105 , B60R2300/303 , B60R2300/306 , B60R2300/605 , B60R2300/70 , H04N13/239 , H04N2213/001
Abstract: An in-vehicle image processing device capable of appropriately monitoring areas forward of, around, and rearward of a vehicle is provided at low cost. The device is for mounting on a vehicle and includes a camera, an image processing unit, and a determination unit. With a reflector provided in front of the camera, the camera can image, for display in a frame at a time, a first area forward of the vehicle and a second area, e.g. an area around the vehicle. In the image processing unit supplied with such image data from the camera, either the first-area image or the second-area image is appropriately processed whereas image processing is omitted for the other image. Alternatively, both images are subjected to a same image processing. The determination unit supplied with vehicle speed information supplies appropriate control instruction information based on the current vehicle speed to the image processing unit.
Abstract translation: 能够以低成本提供能够适当地监视车辆前方，后方和后方的区域的车载图像处理装置。 该装置用于安装在车辆上并且包括相机，图像处理单元和确定单元。 使用设置在相机前面的反射器，相机可以一次成像在一帧中的第一区域，第二区域（例如，第二区域）。 车辆周围的一个区域。 在从相机提供这样的图像数据的图像处理单元中，对第一区域图像或第二区域图像进行适当处理，而对于另一图像省略图像处理。 或者，对两个图像进行相同的图像处理。 提供有车速信息的确定单元将基于当前车速的适当的控制指令信息提供给图像处理单元。
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Patent Agency Ranking
公开(公告)号：US20250159363A1
公开(公告)日：2025-05-15
申请号：US18925421
申请日：2024-10-24
Applicant: Renesas Electronics Corporation
Inventor： Kazuaki TERASHIMA , Isao NAGAYOSHI
Abstract: A semiconductor device capable of verifying whether or not correct acquirement of image data from a sensor has been successful is provided. A semiconductor device includes: a reception interface circuit receiving a plurality of packets including a plurality of line data, respectively, and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data; and a capture circuit provided at a subsequent stage of the reception interface circuit. The capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.
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公开(公告)号：US20240104018A1
公开(公告)日：2024-03-28
申请号：US18347148
申请日：2023-07-05
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuaki TERASHIMA
IPC: G06F12/0831 , G06F13/28
CPC classification number: G06F12/0835 , G06F13/28
Abstract: A second memory stores a plurality of input data sets DSi composed of a plurality of pieces of input data. N multiply-accumulate units are capable of performing parallel processings, and each performs a multiply-accumulate operation on any one of the plurality of weight parameter sets and any one of the plurality of input data sets. A second DMA controller transfers the input data set from the second memory to the n multiply-accumulate units. A measurement circuit measures a degree of matching/mismatching of logic levels among the plurality of pieces of input data contained in the input data set within the memory MEM2, the sequence controller controls the number of parallel processings by the n multiply-accumulate units based on a measurement result by the measurement circuit.
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公开(公告)号：US20230297528A1
公开(公告)日：2023-09-21
申请号：US18152582
申请日：2023-01-10
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazuaki TERASHIMA , Atsushi NAKAMURA , Rajesh GHIMIRE
CPC classification number: G06F13/28 , G06F13/1689 , G06F7/5443
Abstract: A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.
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公开(公告)号：US20170278214A1
公开(公告)日：2017-09-28
申请号：US15422700
申请日：2017-02-02
Applicant: Renesas Electronics Corporation
Inventor： Kazuaki TERASHIMA , Yuki KAJIWARA
CPC classification number: G06T1/20 , G05D1/0246 , H04N13/207
Abstract: Image processing is made efficient. An image processing apparatus according to an embodiment includes a line memory, a plurality of pipelines, and a line memory control circuit that controls data reading from the line memory to processing units. The processing unit includes a first operator that performs a first arithmetic operation, a second operator which performs a second arithmetic operation based on first intermediate data based on an arithmetic operation result of the first operator and which calculates second intermediate data according to the first intermediate data of when peripheral pixels are sequentially changed, third operators which perform a third arithmetic operation based on the first intermediate data and which calculate third intermediate data according to the first intermediate data of when the peripheral pixels are sequentially changed, and delay elements that delay the third intermediate data.
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公开(公告)号：US20240419605A1
公开(公告)日：2024-12-19
申请号：US18646506
申请日：2024-04-25
Applicant: Renesas Electronics Corporation
Inventor： Ryuichi IGARASHI , Katsushige MATSUBARA , Kazuaki TERASHIMA
IPC: G06F12/1045 , G06F7/544 , G06F12/06
Abstract: A semiconductor device includes a scratchpad memory, a memory controller, and a MAC (multiply-accumulation) unit. The scratchpad memory is configured to store image data of N channels and includes M memories which are individually accessible, wherein M is integer of at least 2 and N is an integer of at least 2. The memory controller controls access to the scratchpad memory such that pixel data of the N channels which are arranged at a same position in image data of the N channels are respectively stored in difference memories in the M memories. The MAC unit includes a plurality of calculators to calculate pixel data of the N channels read from the scratchpad memory by using the memory controller and a weight parameter.
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