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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    半导体集成电路设备

    公开(公告)号：US20160071572A1

    公开(公告)日：2016-03-10

    申请号：US14942130

    申请日：2015-11-16

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Natsuki IKEHATA ,  Kazuo TANAKA ,  Takeo TOBA ,  Masashi ARAKAWA

    IPC: G11C11/4091 ,  G11C11/4076

    CPC classification number: G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

    Abstract translation: 差分放大电路的输出信号特性得到改善。 当输入数据信号变为“低”时，流过第一晶体管的电流将减小，并且第一电阻和第二电阻之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为“高”时，第一晶体管的电流增加，因此节点处的电位减小。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20130264647A1

    公开(公告)日：2013-10-10

    申请号：US13910891

    申请日：2013-06-05

    Applicant: Renesas Electronics Corporation

    Inventor： Takeo TOBA ,  Kazuo TANAKA ,  Hiroyasu ISHIZUKA

    IPC: H01L27/02

    CPC classification number: H01L27/0292 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0251 ,  H01L27/11898 ,  H01L2224/05553 ,  H01L2224/06 ,  H01L2924/1301 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

    Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

    Abstract translation: 一种具有“I / O单元上的PAD”结构的半导体集成电路器件，其中焊盘引线部分几乎位于I / O部分的中心，以便减小芯片布局面积。 在I / O部分中，晶体管最靠近半导体芯片的外围。 当在I / O部分的平面图中看到时，电阻位于晶体管的上方，并且第一和第二二极管位于电阻之上; 第二晶体管位于二极管之上; 并且逻辑块位于第二晶体管的上方，其间具有形成在金属布线层中的焊盘引线部分。 这允许通过第二晶体管的焊盘在相同的节点上，因此焊盘引线部分可以几乎位于I / O部分的中心。

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