公开(公告)号：US10003345B2

公开(公告)日：2018-06-19

申请号：US14966343

申请日：2015-12-11

申请人： Research & Business Foundation Sungkyunkwan University

发明人： Kang Yoon Lee ,  Sang Yun Kim ,  In Seong Kim ,  Seong Jin Oh ,  Dong Soo Lee

IPC分类号： H03L7/10 ,  H03L7/08 ,  H03L7/23 ,  H03L7/18 ,  H03L7/089 ,  H03L7/087 ,  H04L7/033 ,  H04L7/10

CPC分类号： H03L7/10 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/089 ,  H03L7/18 ,  H03L7/23 ,  H04L7/033 ,  H04L7/10

摘要： A clock and data recovery circuit is disclosed herein. The clock and data recovery circuit includes a phase detection unit, a charge pump, a loop filter, a voltage control oscillator, and a frequency detection unit. The voltage control oscillator has oscillation frequency that is variable in response to a frequency adjustment signal, and outputs an oscillation signal. The frequency detection unit includes a reference clock divider, a counter, and an oscillation frequency control unit. The reference clock divider generates a count-enable signal based on a reference clock signal. The counter generates an oscillation count signal by counting the pulses of the oscillation signal of the voltage control oscillator or the pulses of divided signals resulting from dividing the oscillation signal while the count-enable signal is being enabled. The oscillation frequency control unit compares a target count value with the value of the oscillation count signal, and outputs the frequency adjustment signal.

公开(公告)号：US09577575B2

公开(公告)日：2017-02-21

申请号：US14966294

申请日：2015-12-11

申请人： Research & Business Foundation Sungkyunkwan University

发明人： Kang Yoon Lee ,  Sang Yun Kim ,  Young Jun Park ,  Dong Soo Lee

IPC分类号： H03K21/00 ,  H03B19/14 ,  H03K3/03

CPC分类号： H03B19/14 ,  H03B2200/007 ,  H03B2200/0074 ,  H03K3/0315 ,  H03K3/0322

摘要： An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal. The variable load resistor control unit compares target count values, determined based on the target frequencies of the divided output signals, with the divided output count signals, and outputs the resistance adjustment signal.

摘要翻译： 公开了一种注入锁定分频器。 注入锁定分频器包括子谐波注入锁定振荡器，参考时钟分频器，计数器和可变负载电阻控制单元。 子谐波注入锁定振荡器具有响应于电阻调节信号而调节的可变负载电阻器，并且当基于可变负载电阻器的幅度确定的振荡频率是喷射信号的次谐波时，输出信号 具有作为分频输出信号的振荡频率。 参考时钟分频器根据参考分频比从参考时钟信号产生计数使能信号。 计数器响应于计数使能信号，基于划分的输出信号产生分割的输出计数信号。 可变负载电阻控制单元将根据划分的输出信号的目标频率确定的目标计数值与划分的输出计数信号进行比较，并输出电阻调节信号。