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公开(公告)号：US20050033898A1
公开(公告)日：2005-02-10
申请号：US10636984
申请日：2003-08-07
CPC分类号： G11C29/32 , G11C2029/3202
摘要： The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory elements is cleared. Second, the desired values are loaded into the scan memory elements. Third, the values from the scan memory elements are propagated to the non-scan memory elements.
摘要翻译： 本发明提供了一种用于将值有效地加载到扫描和非扫描存储器元件中的方法和装置。 首先，用于将控制信号分配给存储器元件的网络被清除。 其次，将期望的值加载到扫描存储器元件中。 第三，来自扫描存储器元件的值被传播到非扫描存储器元件。
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公开(公告)号：US07447960B2
公开(公告)日：2008-11-04
申请号：US10636984
申请日：2003-08-07
IPC分类号： G01R31/3177 , G01R31/316
CPC分类号： G11C29/32 , G11C2029/3202
摘要： The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory elements is cleared. Second, the desired values are loaded into the scan memory elements. Third, the values from the scan memory elements are propagated to the non-scan memory elements.
摘要翻译： 本发明提供了一种用于将值有效地加载到扫描和非扫描存储器元件中的方法和装置。 首先，用于将控制信号分配给存储器元件的网络被清除。 其次，将期望的值加载到扫描存储器元件中。 第三，来自扫描存储器元件的值被传播到非扫描存储器元件。
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公开(公告)号：US07213220B2
公开(公告)日：2007-05-01
申请号：US11009350
申请日：2004-12-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to the field of computer hardware locic circuits, and in particular to a method for verifying the proper operation of a digital logic circuit, and in particular to symbolic simulation of a gate-level netlist corresponding to said hardware logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) analyzing symbolic expressions visible at predetermined locations within said logic; b) determining, which nets in the netlist carry complex symbolic expressions, which comprise more than one symbol; c) replacing said complex expressions with a “crunshed color”, for cutting off said complex symbolic expression from further propagation through the netlist; d) continuing said symbolic simulation including said crunched color information on predetermined nets.
摘要翻译： 本发明涉及计算机硬件定位电路领域，特别涉及用于验证数字逻辑电路的正确操作的方法，特别涉及对应于所述硬件逻辑电路的门级网表的符号仿真。 为了在功能，详尽的仿真和符号仿真领域增加一个有用的替代方案，提出了执行以下步骤：a）分析在所述逻辑内的预定位置可见的符号表达式; b）确定网表中的网络携带多于一个符号的复杂符号表达式; c）用“重要颜色”代替所述复合表达式，以便将所述复杂符号表达式从进一步传播通过网表切断; d）继续所述符号模拟，其包括在预定网上的所述嘎吱嘎吱的颜色信息。
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公开(公告)号：US07565636B2
公开(公告)日：2009-07-21
申请号：US12060953
申请日：2008-04-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefore. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.
摘要翻译： 本发明涉及一种用于验证数字逻辑电路和程序产品的正确操作的系统。 为了在功能，详尽的仿真和符号仿真领域添加有用的替代方案，提出了执行以下步骤：a）用除位值之外的附加属性标记网，其中所述位值和 所述额外财产在特定时间在所述净值有效; b）根据一组预定的语义规则传播网络的标记，其中根据预定的模拟定义所述一组预定语义规则; 以及c）在所述数字逻辑电路的预定下游位置处产生输出，所述输出提供信息，如果或者不是所述属性已经通过所述电路传播到所述预定下游位置。
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5.发明授权Method of improving logical built-in self test (LBIST) AC fault isolations 失效改进逻辑内置自检（LBIST）交流故障隔离的方法公开(公告)号：US07376875B2
公开(公告)日：2008-05-20
申请号：US11181406
申请日：2005-07-14
IPC分类号： G01R31/28
CPC分类号： G01R31/318566 , G01R31/318536
摘要： A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to locate a first latch that fails the test. Particularly, latches on the chip are arranged in a plurality of scan chains wherein each latch holds data for a logical cone. The LBIST is performed on one scan chain at a time. Once the first latch is located, a first limiting cone (i.e., the cone for which the first latch is holding data) may be isolated. After isolating the first limiting cone, the data from the first latch is masked out and the LBIST is repeated on the scan chain. The data is masked out in order to facilitate the identification of any other latch that may fail the test. Again, if another latch fails the test a corresponding limiting cone may be isolated.
摘要翻译： 提供了一种在逻辑内置自检（LBIST）期间隔离芯片中的多个限制性逻辑锥的系统，装置和方法。 在芯片上执行LBIST，以便定位测试失败的第一个锁存器。 特别地，芯片上的锁存器被布置在多个扫描链中，其中每个锁存器保存用于逻辑锥的数据。 LBIST一次在一个扫描链上执行。 一旦位于第一锁存器中，可以隔离第一限位锥（即，第一锁存器保持数据的锥）。 隔离第一个限制锥后，第一个锁存器的数据被屏蔽，LBIST在扫描链上重复。 数据被屏蔽，以便于识别任何其他可能未通过测试的锁存器。 再次，如果另一个闩锁失败，则可以隔离相应的限制锥。
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6.发明授权Method for parallel simulation on a single microprocessor using meta-models 有权使用元模型对单个微处理器进行并行仿真的方法公开(公告)号：US07353159B2
公开(公告)日：2008-04-01
申请号：US10146331
申请日：2002-05-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch (24,26). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.
摘要翻译： 本发明一般涉及硬件开发和设计，特别涉及一种用于模拟硬件的方法。 编辑元模型（22）用于集成相同硬件模型的多个n个不同实例（12A，...，12N），并且不同实例的设施和信号通过实例化特定名称空间规范来解析 代码开关（24,26）。 因此，通过模拟元模型，节省了计算时间，更有效地利用处理器资源，例如存储空间。
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7.发明授权Method and system for formal unidirectional bus verification using synthesizing constrained drivers 有权使用合成约束驱动程序进行正式单向总线验证的方法和系统公开(公告)号：US07305636B2
公开(公告)日：2007-12-04
申请号：US11065601
申请日：2005-02-24
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G06F17/5022 , G06F17/504
摘要： A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal equivalence is evaluated on the testbench to perform verification.
摘要翻译： 公开了一种用于执行验证的方法，系统和计算机程序产品。 创建对设计的高级描述，并从设计的高级描述合成约束的驱动程序。 测试台是从设计的高级描述和受限制的驱动程序生成的，并且在测试台上进行正式的等效性来执行验证。
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8.发明申请公开(公告)号：US20070089004A1
公开(公告)日：2007-04-19
申请号：US11252512
申请日：2005-10-18
IPC分类号： G01R31/28
CPC分类号： G06F17/5022 , G01R31/318357
摘要： The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OCPG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.
摘要翻译： 本发明提供一种用于对TTP-LBIST应用外部时钟和数据模式的方法，装置和计算机程序产品。 在仿真器中设置了被测逻辑的仿真模型。 接下来，用户设置外部LBIST块，其包括预先验证的内部时钟和数据模式逻辑，并将该块连接到仿真模型中的逻辑。 内部时钟和数据模式逻辑提供了LBIST的OCPG模式中使用的输入模式。 该内部时钟和数据模式逻辑已经通过设计工作进行了验证。 因此，内部模式发生器成为模拟模型中的外部模式发生器。 外部LBIST块应用外部时钟和数据模式，随后用户接收并处理这些输出模式以确定逻辑是否正常工作。
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公开(公告)号：US20080195339A1
公开(公告)日：2008-08-14
申请号：US12102510
申请日：2008-04-14
IPC分类号： G01R31/00
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译： 公开了一种用于进行时间检查的装置。 用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。 在测试期间，信号记录器耦合到被测设备（DUT）。 每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。 每个计数模块与边缘检测模块之一相关联。 每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。 在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。
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10.发明申请SYSTEM AND APPARATUS FOR IMPROVING LOGICAL BUILT-IN SELF TEST (LBIST) AC FAULT ISOLATIONS 审中-公开用于改进逻辑内置自检（LBIST）交流故障隔离的系统和设备公开(公告)号：US20080189584A1
公开(公告)日：2008-08-07
申请号：US12060405
申请日：2008-04-01
CPC分类号： G01R31/318566 , G01R31/318536
摘要： A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to locate a first latch that fails the test. Particularly, latches on the chip are arranged in a plurality of scan chains wherein each latch holds data for a logical cone. The LBIST is performed on one scan chain at a time. Once the first latch is located, a first limiting cone (i.e., the cone for which the first latch is holding data) may be isolated. After isolating the first limiting cone, the data from the first latch is masked out and the LBIST is repeated on the scan chain. The data is masked out in order to facilitate the identification of any other latch that may fail the test. Again, if another latch fails the test a corresponding limiting cone may be isolated.
摘要翻译： 提供了一种在逻辑内置自检（LBIST）期间隔离芯片中的多个限制性逻辑锥的系统，装置和方法。 在芯片上执行LBIST，以便定位测试失败的第一个锁存器。 特别地，芯片上的锁存器被布置在多个扫描链中，其中每个锁存器保存用于逻辑锥的数据。 LBIST一次在一个扫描链上执行。 一旦位于第一锁存器中，可以隔离第一限位锥（即，第一锁存器保持数据的锥）。 隔离第一个限制锥后，第一个锁存器的数据被屏蔽，LBIST在扫描链上重复。 数据被屏蔽，以便于识别任何其他可能未通过测试的锁存器。 再次，如果另一个闩锁失败，则可以隔离相应的限制锥。
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