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    Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory
    2.
    发明授权
    Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory 失效
    在分布式存储器多处理系统中的消息传递，其具有用于原子控制消息存储队列在本地存储器中的尾部指针结构的壳体电路

    公开(公告)号：US5841973A

    公开(公告)日：1998-11-24

    申请号：US615694

    申请日：1996-03-13

    申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott

    发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott

    IPC分类号： G06F15/173 ,  G06F13/38 ,  G06F15/16

    CPC分类号： G06F15/17381

    摘要： A messaging facility in a multiprocessor computer system includes assembly circuitry in a source processing element for assembling a message to be sent from the source processing element to a destination processing element based on information provided from a processor in the source processing element. A network router transmits the assembled message from the source processing element to the destination processing element via an interconnect network. A message queue in a local memory of the destination processing element stores the transmitted message. A control word stored in the local memory of the destination processing element includes a limit field designating a size of the message queue and a tail field designating an index into the corresponding message queue to indicate a location in the message queue where the transmitted message is to be stored. Shell circuitry in the destination processing element atomically reads and updates the tail field.

    摘要翻译： 多处理器计算机系统中的消息传递设备包括源处理元件中的组装电路，用于根据源处理元件中的处理器提供的信息来组装要从源处理元件发送到目的地处理元件的消息。 网络路由器经由互连网络将组合的消息从源处理元件发送到目的地处理元件。 目的地处理元件的本地存储器中的消息队列存储发送的消息。 存储在目的地处理元件的本地存储器中的控制字包括指定消息队列的大小的限制字段和指定对应消息队列中的索引的尾部字段，以指示消息队列中发送的消息所在的位置 存储。 目标处理元件中的Shell电路原子地读取和更新尾部字段。

    Stream buffers for high-performance computer memory system
    3.
    发明授权
    Stream buffers for high-performance computer memory system 失效
    流缓冲区用于高性能计算机内存系统

    公开(公告)号：US5761706A

    公开(公告)日：1998-06-02

    申请号：US333133

    申请日：1994-11-01

    申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Subbarao Palacharla

    发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Subbarao Palacharla

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6026

    摘要： Method and apparatus for a filtered stream buffer coupled to a memory and a processor, and operating to prefetch data from the memory. The filtered stream buffer includes a cache block storage area and a filter controller. The filter controller determines whether a pattern of references has a predetermined relationship, and if so, prefetches stream data into the cache block storage area. Such stream data prefetches are particularly useful in vector processing computers, where once the processor starts to fetch a vector, the addresses of future fetches can be predicted based in the pattern of past fetches. According to various aspects of the present invention, the filtered stream buffer further includes a history table, a validity indicator which is associated with the cache block storage area and indicates which cache blocks, if any, are valid. According to yet another aspect of the present invention, the filtered stream buffer controls random access memory (RAM) chips to stream the plurality of consecutive cache blocks from the RAM into the cache block storage area. According to yet another aspect of the present invention, the stream data includes data for a plurality of strided cache blocks, wherein each of which these strided cache blocks corresponds to an address determined by adding to the first address an integer multiple of the difference between the second address and the first address. According to yet another aspect of the present invention, the processor generates three addresses of data words in the memory, and the filter controller determines whether a predetermined relationship exists among three addresses, and if so, prefetches strided stream data into said cache block storage area.

    摘要翻译： 耦合到存储器和处理器的经滤波的流缓冲器的方法和装置，并且用于从存储器预取数据。 滤波的流缓冲器包括高速缓存块存储区域和过滤器控制器。 滤波器控制器确定引用模式是否具有预定关系，如果是，则将流数据预取到高速缓存块存储区域中。 这样的流数据预取在向量处理计算机中特别有用，其中一旦处理器开始获取向量，可以基于过去提取的模式来预测未来提取的地址。 根据本发明的各个方面，滤波流缓冲器还包括历史表，与高速缓存块存储区相关联的有效性指示符，并指示哪些高速缓存块（如果有的话）是有效的。 根据本发明的另一方面，滤波流缓冲器控制随机存取存储器（RAM）芯片以将多个连续高速缓存块从RAM流入高速缓存块存储区域。 根据本发明的另一方面，流数据包括用于多个跨度高速缓存块的数据，其中这些跨越高速缓存块中的每一个对应于通过将第一地址相加的确定的地址， 第二个地址和第一个地址。 根据本发明的另一方面，处理器在存储器中产生数据字的三个地址，并且滤波器控制器确定在三个地址之间是否存在预定的关系，如果是，则将步进流数据预取到所述高速缓存块存储区域 。

    Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller
    5.
    发明授权
    Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller 失效
    使用两条数据路径的大规模并行处理系统：一条将路由器电路连接到互连网络，另一条连接路由器电路连接到I / O控制器

    公开(公告)号：US5864738A

    公开(公告)日：1999-01-26

    申请号：US614859

    申请日：1996-03-13

    申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott

    发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott

    IPC分类号： G06F12/08 ,  G06F15/173 ,  G06F15/80 ,  G06G13/00

    CPC分类号： G06F15/17375 ,  G06F12/0817 ,  G06F15/8007

    摘要： A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory. Each router circuit includes means for transferring data between the processor and the interconnect network and means for transferring data between the local memory and the interconnect network. An I/O controller is connected to a plurality of the router circuits. Data is then read from the peripheral device and transferred through the I/O controller to local memory of one of the processing elements.

    摘要翻译： 在具有互连网络和多个处理节点的外围设备和MPP系统之间传送信息的系统和方法。 每个处理元件包括处理器，本地存储器和连接到互连网络的路由器电路，处理器和本地存储器。 每个路由器电路包括用于在处理器和互连网络之间传送数据的装置和用于在本地存储器和互连网络之间传送数据的装置。 I / O控制器连接到多个路由器电路。 然后从外围设备读取数据，并通过I / O控制器传送到其中一个处理元件的本地存储器。

    Barrier and eureka synchronization architecture for multiprocessors
    8.
    发明授权
    Barrier and eureka synchronization architecture for multiprocessors 失效
    多处理器的屏障和尤里卡同步架构

    公开(公告)号：US5721921A

    公开(公告)日：1998-02-24

    申请号：US450251

    申请日：1995-05-25

    申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Gregory M. Thorson

    发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Gregory M. Thorson

    IPC分类号： G06F9/46 ,  G06F13/38 ,  G06F15/16

    CPC分类号： G06F9/52

    摘要： Method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping barrier/eureka synchronization partitions are available simultaneously through the use of a plurality of parallel barrier/eureka synchronization domains. The present barrier/eureka mechanism may be implemented on either a dedicated barrier network, or superimposed as a virtual barrier/eureka network operating on a physical data-communications network which is also used for data interchange, operating system functions, and other purposes.

    摘要翻译： 用于在大规模并行处理系统中促进障碍和尤里卡同步的方法和装置。 当前的屏障/尤里卡机制提供了一种可分割的，低延迟的，立即可重用的鲁棒机制，其可以在物理数据通信网络上操作，并且可以用于警告分区中的所有处理器实体（PE），当所有PE 该分区已经到达其个别程序代码中的指定障碍点，或者当该分区中的任何一个PE在其各自的程序代码中达到指定的尤里卡点时，或者当满足屏障或尤里卡要求时，哪一个 先到 多个重叠的屏障/尤里卡同步分区可以通过使用多个并行屏障/尤里卡同步域来同时获得。 本势垒/尤里卡机制可以在专用屏障网络上实现，或者叠加在操作在物理数据通信网络上的虚拟屏障/尤里卡网络上，物理数据通信网络也用于数据交换，操作系统功能和其他目的。

    System and method for fault-tolerant transmission of data within a dual ring network
    10.
    发明授权
    System and method for fault-tolerant transmission of data within a dual ring network 失效
    双环网络中数据容错传输的系统和方法

    公开(公告)号：US06233704B1

    公开(公告)日：2001-05-15

    申请号：US08614860

    申请日：1996-03-13

    申请人： Steven L. Scott ,  Steven M. Oberlin ,  Daniel L. Kunkel ,  Gerald A. Schwoerer

    发明人： Steven L. Scott ,  Steven M. Oberlin ,  Daniel L. Kunkel ,  Gerald A. Schwoerer

    IPC分类号： G06F1300

    CPC分类号： G06F13/426

    摘要： A multiple counter-rotating ring computer network system having a permission control scheme for client isolation. The peripheral channel allows two rings to be folded into one longer ring so that faulty nodes can be effectively removed from the network. Or, any of the rings can be masked so that they are unoperational. The network system also allows several client isolation states ranging from complete isolation to master access. These types of isolation allow faulty client devices to be tested while maintaining a high-level of network security by configuring the client to an appropriate isolation state.

    摘要翻译： 具有用于客户端隔离的许可控制方案的多个反向旋转环计算机网络系统。 外围通道允许将两个环折叠成一个较长的环，从而可以有效地从网络上移除故障节点。 或者，任何一个戒指都可以被遮蔽，以使它们不可操作。 网络系统还允许从完全隔离到主访问的多个客户端隔离状态。 这些类型的隔离允许通过将客户端配置为适当的隔离状态来维护高级别的网络安全性来测试故障客户端设备。