公开(公告)号：US06888730B2

公开(公告)日：2005-05-03

申请号：US10084619

申请日：2002-02-28

申请人： Richard Foss ,  Charles Taylor ,  Curtis Richardson

发明人： Richard Foss ,  Charles Taylor ,  Curtis Richardson

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： A content addressable memory (CAM) having a plurality of ternary memory cells, each ternary half cell comprising an equal number of transistors of a p-type and an n-type, the p-type transistors being formed in a first well region and the n-type transistors being formed in a second well region, the wells having at most one p+ to n+ region spacing, the transistors being interconnected to form the half ternary CAM cell and wherein the interconnections for the cell is restricted to a silicon layer and a first metal layer and connections between said cell and external signal lines is restricted to at least a second metal layer.

摘要翻译： 一种具有多个三元存储器单元的内容可寻址存储器（CAM），每个三进制半单元包括相等数量的p型和n型晶体管，所述p型晶体管形成在第一阱区中，并且 n型晶体管形成在第二阱区中，阱具有至多一个p +至n +区间隔，晶体管互连以形成半三元CAM单元，并且其中用于单元的互连限于硅层和 第一金属层和所述电池与外部信号线之间的连接限于至少第二金属层。

公开(公告)号：US20100299424A1

公开(公告)日：2010-11-25

申请号：US12681242

申请日：2008-10-02

申请人： Robby Gurdan ,  Richard Foss

发明人： Robby Gurdan ,  Richard Foss

IPC分类号： G06F15/173

CPC分类号： H04L12/4637 ,  G10H1/0066 ,  G10H1/46 ,  H04H60/04 ,  H04L67/125 ,  H04L67/28 ,  H04L67/2823 ,  H04L69/16 ,  H04L69/26 ,  H04N21/23602 ,  H04N21/2381 ,  H04N21/4342 ,  H04N21/4345 ,  H04N21/4381

摘要： An apparatus for modifying a command message (CMD) received from a source apparatus to control a target device parameter of a target apparatus within a digital multimedia network, wherein a hierarchical parameter address (HPA) or a parameter value contained in said command message (CMD) is changed according to at least one change script to provide a modified command message (CMD').

摘要翻译： 一种用于修改从源设备接收的命令消息（CMD）的设备，用于控制数字多媒体网络内的目标设备的目标设备参数，其中分层参数地址（HPA）或包含在所述命令消息（CMD）中的参数值 ）根据至少一个改变脚本被改变以提供修改的命令消息（CMD'）。

公开(公告)号：US20100290486A1

公开(公告)日：2010-11-18

申请号：US12681208

申请日：2008-10-02

申请人： Robby Gurdan ,  Richard Foss

发明人： Robby Gurdan ,  Richard Foss

IPC分类号： H04J3/06

CPC分类号： H04L12/4637 ,  G10H1/0066 ,  G10H1/46 ,  H04H60/04 ,  H04L67/125 ,  H04L67/28 ,  H04L67/2823 ,  H04L69/16 ,  H04L69/26 ,  H04N21/23602 ,  H04N21/2381 ,  H04N21/4342 ,  H04N21/4345 ,  H04N21/4381

摘要： The present invention relates to a digital multimedia network 1 with latency control comprising apparatuses for processing of data streams, wherein a borderline input apparatus providing a data stream generates a latency time stamp (LTS) which contains an absolute time indicating a creation time of said data stream and an accumulated delay time which is updated by each apparatus processing said data stream, wherein said latency time stamp (LTS) of said data stream is evaluated by a borderline output apparatus of said network which synchronizes said data stream.

摘要翻译： 本发明涉及具有等待时间控制的数字多媒体网络1，其包括用于处理数据流的装置，其中提供数据流的边界线输入装置产生等待时间戳（LTS），其包含指示所述数据的创建时间的绝对时间 流和由每个处理所述数据流的设备更新的累积延迟时间，其中所述数据流的所述等待时间戳（LTS）由同步所述数据流的所述网络的边界输出设备来评估。

公开(公告)号：US07350137B2

公开(公告)日：2008-03-25

申请号：US11313661

申请日：2005-12-22

申请人： Richard Foss ,  Alan Roth

发明人： Richard Foss ,  Alan Roth

IPC分类号： G11C29/00

CPC分类号： G06F11/1064 ,  G11C15/00

摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit, if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.

摘要翻译： 提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。 阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。 该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读出并产生第一多个比特的奇偶校验，并且如果生成和存储的奇偶校验位不匹配，则将生成的奇偶校验与存储的行奇偶校验位进行比较，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

公开(公告)号：US20070200611A1

公开(公告)日：2007-08-30

申请号：US11701924

申请日：2007-02-02

申请人： Richard Foss ,  Peter Gillingham ,  Robert Harland ,  Valerie Lines

发明人： Richard Foss ,  Peter Gillingham ,  Robert Harland ,  Valerie Lines

IPC分类号： G05F3/30

CPC分类号： G11C5/145 ,  G05F3/205 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  H02M3/07

摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

摘要翻译： 一种用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储字线。 升压电路中的晶体管完全切换，从而消除通过晶体管的升压电压降低V th。 升压电容器通过V dd进行充电。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

公开(公告)号：US20060028899A1

公开(公告)日：2006-02-09

申请号：US11113816

申请日：2005-04-25

申请人： Richard Foss ,  Peter Gillingham ,  Robert Harland ,  Valerie Lines

发明人： Richard Foss ,  Peter Gillingham ,  Robert Harland ,  Valerie Lines

IPC分类号： G11C8/00

CPC分类号： G11C5/145 ,  G05F3/205 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  H02M3/07

摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

摘要翻译： 一种用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储字线。 升压电路中的晶体管完全切换，从而消除通过晶体管的升压电压降低V th。 升压电容器通过V dd进行充电。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

公开(公告)号：US06873532B2

公开(公告)日：2005-03-29

申请号：US10351593

申请日：2003-01-27

申请人： Richard Foss

发明人： Richard Foss

IPC分类号： G11C15/00 ,  G11C15/04 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C15/04

摘要： A CAM cell comprises a pair of SRAM cells, each of which comprise a pair of cross coupled inverters for storing a data value and a pair of access devices for accessing a complementary pair of bit lines. The CAM cell ether comprises a pair of compare circuits, each for comparing said data value stored in one of said SRAM cells with a search data value provided on a corresponding search line. The CAM cell has an equivalent number of n-channel and p-channel devices. The CAM cell uses p-channel transistors as access transistors to the SRAM cells in order to improve the efficiency of the layout of the cell array. The implementation ensures a balanced number of p-channel and n-channel devices per cell while still providing excellent functional characteristics.

摘要翻译： CAM单元包括一对SRAM单元，每个SRAM单元包括一对交叉耦合的反相器，用于存储数据值和一对访问器件，用于访问互补的位线对。 CAM单元以太网包括一对比较电路，每对比较电路用于将存储在所述SRAM单元之一中的所述数据值与对应的搜索线上提供的搜索数据值进行比较。 CAM单元具有等效数量的n沟道和p沟道器件。 CAM单元使用p沟道晶体管作为SRAM单元的存取晶体管，以便提高单元阵列布局的效率。 该实现确保了每个单元平衡数量的p沟道和n沟道器件，同时仍然提供出色的功能特性。

公开(公告)号：US10327089B2

公开(公告)日：2019-06-18

申请号：US15566495

申请日：2016-04-14

申请人： Richard Foss ,  DSP4YOU Ltd.

发明人： Richard Foss ,  Antoine Rouget

IPC分类号： G06F3/01 ,  H04R5/02 ,  H04S7/00 ,  G06F3/0346

摘要： Systems and methods for positioning an output element (102, 602) within a three-dimensional environment (104, 604) are described. Movement data relating to movement of a mobile device (120, 620) is obtained (206, 262). The movement data is mapped (208, 264) to movement of a simulated output element (503) in a virtual environment (505), which simulates the three-dimensional environment. The movement of the simulated output element is associated with movement of an output element within the three-dimensional environment so as to control the position of the output element within the three-dimensional environment. In one exemplary embodiment an output element (102) being a sound source is positioned in a three-dimensional, immersive sound environment (104). In another exemplary embodiment a focal point of a light beam (602) is positioned in a three-dimensional theatrical environment (604). The described systems and methods enable a user to control the real-time and/or recorded position and/or movement of an output element by manipulating the orientation of a mobile device (120, 620).

公开(公告)号：US20100299421A1

公开(公告)日：2010-11-25

申请号：US12681238

申请日：2008-09-23

申请人： Robby Gurdan ,  Richard Foss

发明人： Robby Gurdan ,  Richard Foss

IPC分类号： G06F15/177 ,  G06F15/16

CPC分类号： H04L12/4637 ,  G10H1/0066 ,  G10H1/46 ,  H04H60/04 ,  H04L67/125 ,  H04L67/28 ,  H04L67/2823 ,  H04L69/16 ,  H04L69/26 ,  H04N21/23602 ,  H04N21/2381 ,  H04N21/4342 ,  H04N21/4345 ,  H04N21/4381

摘要： The present invention relates to a digital multimedia network of apparatuses each comprising a control device, wherein a device parameter of an apparatus is controlled by sending a command message (CMD) to said control device of said apparatus containing a tree-structured hierarchical parameter address (HPA) which consists of parameter grouping identifiers each corresponding to a hierarchy level of a predetermined tree-structured parameter hierarchy used for addressing device parameters throughout said digital multimedia network.

摘要翻译： 数字多媒体网络技术领域本发明涉及一种数字多媒体网络，每个装置包括控制装置，其中通过向所述装置的所述控制装置发送命令消息（CMD）来控制装置的装置参数，所述控制装置包含树形结构的分层参数地址 HPA），其由参数分组标识符组成，每个参数分组标识符对应于用于在整个所述数字多媒体网络中寻址设备参数的预定树结构参数层级的层级。

公开(公告)号：US07010741B2

公开(公告)日：2006-03-07

申请号：US10306732

申请日：2002-11-29

申请人： Richard Foss ,  Alan Roth

发明人： Richard Foss ,  Alan Roth

IPC分类号： G11C29/00

CPC分类号： G06F11/1064 ,  G11C15/00

摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit; if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.

摘要翻译： 提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。 阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。 该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读取并生成第一多个比特的奇偶校验，并将所生成的奇偶校验与存储的行奇偶校验位进行比较; 如果生成和存储的奇偶校验位不匹配，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。