公开(公告)号：US20070200611A1

公开(公告)日：2007-08-30

申请号：US11701924

申请日：2007-02-02

申请人： Richard Foss ,  Peter Gillingham ,  Robert Harland ,  Valerie Lines

发明人： Richard Foss ,  Peter Gillingham ,  Robert Harland ,  Valerie Lines

IPC分类号： G05F3/30

CPC分类号： G11C5/145 ,  G05F3/205 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  H02M3/07

摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

摘要翻译： 一种用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储字线。 升压电路中的晶体管完全切换，从而消除通过晶体管的升压电压降低V th。 升压电容器通过V dd进行充电。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

公开(公告)号：US20060028899A1

公开(公告)日：2006-02-09

申请号：US11113816

申请日：2005-04-25

申请人： Richard Foss ,  Peter Gillingham ,  Robert Harland ,  Valerie Lines

发明人： Richard Foss ,  Peter Gillingham ,  Robert Harland ,  Valerie Lines

IPC分类号： G11C8/00

CPC分类号： G11C5/145 ,  G05F3/205 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  H02M3/07

摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

摘要翻译： 一种用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储字线。 升压电路中的晶体管完全切换，从而消除通过晶体管的升压电压降低V th。 升压电容器通过V dd进行充电。 调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

公开(公告)号：US07382638B2

公开(公告)日：2008-06-03

申请号：US11774881

申请日：2007-07-09

申请人： Stanley Jeh-Chun Ma ,  Peter P. Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

发明人： Stanley Jeh-Chun Ma ,  Peter P. Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C15/04 ,  G11C15/043

摘要： A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

摘要翻译： 公开了一种用于检测CAM阵列的匹配线上的上升电压的匹配线检测电路。 在开启电流源以将电流提供给匹配线之前，该电路首先将匹配线预先接地，并提高匹配线的电压。 参考匹配线检测电路产生自定时控制信号以保持电流供应在预定持续时间内接通。 电流源关闭后，匹配线上的感测数据将被锁存，并将匹配线预充电到地。 因为本发明的匹配线检测电路将匹配线预充电到地电而不是电源电压VDD，所以消耗较少的功率。 通过感测匹配线电压升高到n沟道晶体管阈值电位，匹配线感测操作速度增加。

公开(公告)号：US20060083041A1

公开(公告)日：2006-04-20

申请号：US11269659

申请日：2005-11-09

申请人： Stanley Ma ,  Peter Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

发明人： Stanley Ma ,  Peter Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

IPC分类号： G11C15/00

CPC分类号： G11C7/06 ,  G11C15/04 ,  G11C15/043

摘要： A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

摘要翻译： 公开了一种用于检测CAM阵列的匹配线上的上升电压的匹配线检测电路。 在开启电流源以将电流提供给匹配线之前，该电路首先将匹配线预先接地，并提高匹配线的电压。 参考匹配线检测电路产生自定时控制信号以保持电流供应在预定持续时间内接通。 电流源关闭后，匹配线上的感测数据将被锁存，并将匹配线预充电到地。 因为本发明的匹配线检测电路将匹配线预充电到地电而不是电源电压VDD，所以消耗较少的功率。 通过感测匹配线电压升高到n沟道晶体管阈值电位，匹配线感测操作速度增加。

公开(公告)号：US06987682B2

公开(公告)日：2006-01-17

申请号：US10258580

申请日：2001-05-01

申请人： Stanley Jeh-Chun Ma ,  Peter P. Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

发明人： Stanley Jeh-Chun Ma ,  Peter P. Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C15/04 ,  G11C15/043

摘要： A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. the circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

公开(公告)号：US20070258277A1

公开(公告)日：2007-11-08

申请号：US11774881

申请日：2007-07-09

申请人： Stanley Ma ,  Peter Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

发明人： Stanley Ma ,  Peter Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

IPC分类号： G11C15/00

CPC分类号： G11C7/06 ,  G11C15/04 ,  G11C15/043

摘要： A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

摘要翻译： 公开了一种用于检测CAM阵列的匹配线上的上升电压的匹配线检测电路。 在开启电流源以将电流提供给匹配线之前，该电路首先将匹配线预先接地，并提高匹配线的电压。 参考匹配线检测电路产生自定时控制信号以保持电流供应在预定持续时间内接通。 电流源关闭后，匹配线上的感测数据将被锁存，并将匹配线预充电到地。 因为本发明的匹配线检测电路将匹配线预充电到地电而不是电源电压VDD，所以消耗较少的功率。 通过感测匹配线电压升高到n沟道晶体管阈值电位，匹配线感测操作速度增加。

公开(公告)号：US07251148B2

公开(公告)日：2007-07-31

申请号：US11269659

申请日：2005-11-09

申请人： Stanley Jeh-Chun Ma ,  Peter P. Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

发明人： Stanley Jeh-Chun Ma ,  Peter P. Ma ,  Valerie Lines ,  Peter Gillingham ,  Robert McKenzie ,  Abdullah Ahmed

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C15/04 ,  G11C15/043

摘要： A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

摘要翻译： 公开了一种用于检测CAM阵列的匹配线上的上升电压的匹配线检测电路。 在开启电流源以将电流提供给匹配线之前，该电路首先将匹配线预先接地，并提高匹配线的电压。 参考匹配线检测电路产生自定时控制信号以保持电流供应在预定持续时间内接通。 电流源关闭后，匹配线上的感测数据将被锁存，并将匹配线预充电到地。 因为本发明的匹配线检测电路将匹配线预充电到地电而不是电源电压VDD，所以消耗较少的功率。 通过感测匹配线电压升高到n沟道晶体管阈值电位，匹配线感测操作速度增加。

公开(公告)号：US20050265506A1

公开(公告)日：2005-12-01

申请号：US11195257

申请日：2005-08-01

申请人： Richard Foss ,  Peter Gillingham ,  Graham Allan

发明人： Richard Foss ,  Peter Gillingham ,  Graham Allan

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03D3/24 ,  H03K5/13 ,  H03L7/081

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

摘要： A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.

摘要翻译： 包括用于同步存储器的时钟施加电路或用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置，以及用于接收时钟输入信号并用于传送时钟的抽头延迟线 驱动信号与时钟输入信号同步但延迟到同步存储器，延迟是时钟周期或时钟输入信号的一小部分。

公开(公告)号：US08781053B2

公开(公告)日：2014-07-15

申请号：US12168091

申请日：2008-07-04

申请人： Hong Beom Pyeon ,  Peter Gillingham

发明人： Hong Beom Pyeon ,  Peter Gillingham

IPC分类号： H03D3/24

CPC分类号： H04L7/0331 ,  G06F13/1689 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  Y02D10/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped. The devices of one group can be structured by multiple chip packages.

摘要翻译： 系统包括存储器控制器和串联连接的多个半导体器件。 每个设备具有用于存储数据的存储器核心。 存储器控制器提供用于同步器件的操作的时钟信号。 每个器件包括被PLL使能信号选择性地使能或禁止的锁相环（PLL）。 在每个组中，选定数量的器件的PLL通过PLL使能信号使能，其他器件被禁止。 所启用的PLL响应于输入时钟信号提供多个具有90°的倍数的相移的再现时钟信号。 数据传输与再现的时钟信号中的至少一个同步。 在禁用PLL的器件中，数据传输与输入时钟信号同步。 使能的PLL和禁用的PLL分别使器件成为源和公共同步时钟。 设备可以分组。 一组的器件可以由多个芯片封装构成。

公开(公告)号：US08471591B2

公开(公告)日：2013-06-25

申请号：US13284338

申请日：2011-10-28

申请人： Peter Gillingham

发明人： Peter Gillingham

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K3/012 ,  H01L2924/0002 ,  H03K19/0005 ,  H03K19/00361 ,  H04L25/0278 ,  H01L2924/00

摘要： In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.

摘要翻译： 在具有连接到内部部分的端子的半导体器件中，用于为器件的端子提供管芯端接的终端电路。 终端电路包括多个晶体管，其包括连接在端子和电源之间的至少一个NMOS晶体管和至少一个PMOS晶体管; 以及控制电路，用于以相应的NMOS栅极电压驱动每个NMOS晶体管的栅极并且用相应的PMOS栅极电压驱动每个PMOS晶体管的栅极，所述控制电路被配置为控制NMOS和PMOS栅极电压，以便 当使能片上端接时，将晶体管置于欧姆区域。 电源提供小于每个所述NMOS栅极电压并大于每个所述PMOS栅极电压的电压。