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公开(公告)号：US5253129A
公开(公告)日：1993-10-12
申请号：US791792
申请日：1991-11-12
申请人： Richard J. Blackborow , Peter S. Hahn , Claude E. Camp , Donald C. Westwood , Rodica Florea , Eric J. Botto , Scott E. Richmond , David B. Jeppson
发明人： Richard J. Blackborow , Peter S. Hahn , Claude E. Camp , Donald C. Westwood , Rodica Florea , Eric J. Botto , Scott E. Richmond , David B. Jeppson
CPC分类号： G11B33/121 , G06F1/18 , G06F3/0601 , G11B19/02 , G11B25/043 , G11B33/08 , G11B33/14 , G06F2003/0692
摘要： A removable and transportable hard disk subsystem is provided for use with at least one computer and includes at least one hard disk module. The module contains a shock mounted, thin and compact micro-Winchester head and disk assembly which plugs into a base housing which is installable entirely within a well of the computer nominally allotted to receive a 51/4 inch half height disk drive. The base housing includes a head positioning and data module loading/unloading portion of the subsystem control electronics and an electromechanical mechanism for automatically loading and unloading the hard disk module. The base housing provides electrical connections for operating the head and disk assembly when loaded therein. The subsystem further includes an adapter board having a host interface portion of the subsystem control electronics and connected by a cable with the control electronics portion of the base housing, the adapter board for connecting the subsystem directly to address, data and control buses of said computer to enable storage and retrieval in the loaded module of host computer data blocks.
摘要翻译： 提供可移动和可运输的硬盘子系统用于与至少一台计算机一起使用并且包括至少一个硬盘模块。 该模块包含一个冲击安装的，薄而紧凑的微型温彻斯特头和盘组件，其插入基座外壳，该底座外壳可完全安装在名义上分配为接收51/4英寸半高的磁盘驱动器的计算机的一个孔中。 基座壳体包括子系统控制电子装置的头部定位和数据模块装载/卸载部分，以及用于自动加载和卸载硬盘模块的机电机构。 底座外壳提供电气连接，用于在装载其中时操作头部和盘组件。 子系统进一步包括适配器板，其具有子系统控制电子设备的主机接口部分，并通过电缆与基座壳体的控制电子部分连接，用于将子系统直接连接到所述计算机的地址，数据和控制总线的适配器板 以在主机数据块的加载模块中实现存储和检索。
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公开(公告)号：US5065262A
公开(公告)日：1991-11-12
申请号：US585949
申请日：1990-09-21
申请人： Richard J. Blackborow , Peter S. Hahn , Claude E. Camp , Donald C. Westwood , Rodica Florea , Eric J. Botto , Scott E. Richmond , David B. Jeppson
发明人： Richard J. Blackborow , Peter S. Hahn , Claude E. Camp , Donald C. Westwood , Rodica Florea , Eric J. Botto , Scott E. Richmond , David B. Jeppson
CPC分类号： G11B33/121 , G06F1/18 , G06F3/0601 , G11B19/02 , G11B25/043 , G11B33/08 , G11B33/14 , G06F2003/0692 , Y10S360/902 , Y10S360/903
摘要： A removable and transportable hard disk subsystem is provided for use with at least one computer and includes at least one hard disk module. The module contains a shock mounted, thin and compact micro-Winchester head and disk assembly which plugs into a base housing which is installable entirely within a well of the computer nominally allotted to receive a 51/4 inch half height disk drive. The base housing includes a head positioning and data module loading/unloading portion of the subsystem control electronics and an electromechanical mechanism for automatically loading and unloading the hard disk module. The base housing provides electrical connections for operating the head and disk assembly when loaded therein. The subsystem further includes an adapter board having a host interface portion of the subsystem control electronics and connected by a cable with the control electronics portion of the base housing, the adapter board for connecting the subsystem directly to address, data and control buses of said computer to enable storage and retrieval in the loaded module of host computer data blocks.
摘要翻译： 提供可移动和可运输的硬盘子系统用于与至少一台计算机一起使用并且包括至少一个硬盘模块。 该模块包含一个冲击安装的，薄而紧凑的微型温彻斯特头和盘组件，其插入基座外壳，该底座外壳可完全安装在名义上分配为接收51/4英寸半高的磁盘驱动器的计算机的一个孔中。 基座壳体包括子系统控制电子装置的头部定位和数据模块装载/卸载部分，以及用于自动加载和卸载硬盘模块的机电机构。 底座外壳提供电气连接，用于在装载其中时操作头部和盘组件。 子系统进一步包括适配器板，其具有子系统控制电子设备的主机接口部分，并通过电缆与基座壳体的控制电子部分连接，用于将子系统直接连接到所述计算机的地址，数据和控制总线的适配器板 以在主机数据块的加载模块中实现存储和检索。
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公开(公告)号：US5041924A
公开(公告)日：1991-08-20
申请号：US278006
申请日：1988-11-30
申请人： Richard J. Blackborow , Peter S. Hahn , Claude E. Camp , Donald C. Westwood , Rodica Florea , Eric J. Botto , Scott E. Richmond , David B. Jeppson
发明人： Richard J. Blackborow , Peter S. Hahn , Claude E. Camp , Donald C. Westwood , Rodica Florea , Eric J. Botto , Scott E. Richmond , David B. Jeppson
CPC分类号： G11B33/121 , G06F1/18 , G06F3/0601 , G11B19/02 , G11B25/043 , G11B33/08 , G11B33/14 , G06F2003/0692 , Y10S360/902 , Y10S360/903
摘要： A removable and transportable hard disk subsystem is provided for use with at least one computer and includes at least one hard disk module. The module contains a shock mounted, thin and compact micro-Winchester head and disk assembly which plugs into a base housing which is installable entirely within a well of the computer nominally allotted to receive a 51/4 inch half height disk drive. The base housing includes a head positioning and data module loading/unloading portion of the subsystem control electronics and an electromechanical mechanism for automatically loading and unloading the hard disk module. The base housing provides electrical connections for operating the head and disk assembly when loaded therein. The subsystem further includes an adapter board having a host interface portion of the subsystem control electronics and connected by a cable with the control electronics portion of the base housing, the adapter board for connecting the subsystem directly to address, data and control buses of said computer to enable storage and retrieval in the loaded module of host computer data blocks.
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4.发明授权Solid state memory array using address block bit substitution to compensate for non-functional storage cells 失效固态存储器阵列使用地址块位替换来补偿非功能存储单元
公开(公告)号：US5199033A
公开(公告)日：1993-03-30
申请号：US521575
申请日：1990-05-10
IPC分类号： G11C29/00
CPC分类号： G11C29/76
摘要： A solid state memory array includes an address bus and a bidirectional data bus and a plurality of partly defective VLSI memory array chips each containing at least one megabit of data storage capacity, having defective memory cell locations, being connected to the address bus, and providing plural data storage bit positions. Each memory array chip has a bidirectional tri-state driver connected between the bit lines thereof and corresponding ones of the data bus. At least one VLSI substitution memory chip contains at least one megabyte of data storage capacity, is connected to the address bus and provides plural data storage bit positions. A substitution chip tri-state driver is connected between the bit lines of the substitution memory chip and all of the parallel data bit lines of the data bus. A programmable read only memory is connected to be addressed by the address bus and is programmed for putting out a binary coded value which has been coded to identify each said defective memory cell location of each one of the memory array chips. A decoder is connected to receive and decode the binary coded value into tri-state driver control values and applies the values to the substitution chip tri-state driver and to one of the memory array chip bidirectional tri-state drivers so as to disable the memory array chip associated with the particular chip driver when a defective memory cell location thereof is addressed, and to enable the substitution memory chip at the particular location and connect it to the data bus in place of the associated memory array chip.
摘要翻译： 固态存储器阵列包括地址总线和双向数据总线以及多个部分有缺陷的VLSI存储器阵列芯片，每个存储器阵列芯片包含连接到地址总线的具有缺陷存储器单元位置的至少一兆位的数据存储容量，并提供 多个数据存储位位置。 每个存储器阵列芯片具有连接在它们的位线和对应的数据总线之间的双向三态驱动器。 至少一个VLSI替换存储器芯片包含至少一兆字节的数据存储容量，连接到地址总线并提供多个数据存储位位置。 替代芯片三态驱动器连接在替代存储器芯片的位线和数据总线的所有并行数据位线之间。 连接可编程只读存储器以由地址总线寻址，并且被编程为输出已被编码的二进制编码值，以识别存储器阵列芯片中的每一个的每个所述缺陷存储器单元位置。 连接解码器以将二进制编码值接收并解码为三态驱动器控制值，并将该值应用于替代芯片三态驱动器和存储器阵列芯片双向三态驱动器之一，以禁用存储器 阵列芯片与特定芯片驱动器相关联，当其存储器单元的位置不正确时，并且能够使特定位置处的替换存储器芯片并且将其连接到数据总线来代替相关联的存储器阵列芯片。
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公开(公告)号：US5471176A
公开(公告)日：1995-11-28
申请号：US255162
申请日：1994-06-07
CPC分类号： G06F1/08 , H03K3/0315 , H04L7/0083 , H04L7/0337
摘要： A clock generation circuit includes a reference clock for putting out a stable reference clocking signal. A digital ring oscillator includes a series circuit loop having at least one inverting gate and a programmable delay line of plural delays formed a series of tapped digital transmission gates connected between an output and an input of the inverting gate. A multiplexer selects among the series of taps in accordance with a tap selection signal. A clock monitoring circuit is connected to compare the clock output with a stable reference clocking signal to produce a digital clock cycle count. A programmed microcontroller generates the tap selection value as a function of the digital clock cycle count and a desired clock output frequency set point. And, a synchronization circuit synchronizes tap selection value applied to the multiplexer in relation to the present, adjustable clocking signal, and to a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following the tap selection, in order to avoid glitches and without interrupting oscillation.
摘要翻译： 时钟生成电路包括用于输出稳定的参考时钟信号的参考时钟。 数字环形振荡器包括串联电路回路，其具有至少一个反相门和多个延迟的可编程延迟线，形成连接在反相门的输出端和输入端之间的一系列抽头数字传输门。 多路复用器根据抽头选择信号在一系列抽头之间进行选择。 连接时钟监控电路，将时钟输出与稳定的参考时钟信号进行比较，以产生数字时钟周期计数。 编程的微控制器根据数字时钟周期计数和期望的时钟输出频率设定点产生抽头选择值。 并且，同步电路将应用于多路复用器的抽头选择值与当前可调整的时钟信号相同步，并且与随后的数字环形振荡器在抽头选择之后被放出的后继可调时钟信号的逻辑状态同步， 以避免毛刺和不中断振荡。
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