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    OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS
    2.
    发明申请
    OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS 失效
    用于改进联系人的超重压力衬管

    公开(公告)号：US20080237737A1

    公开(公告)日：2008-10-02

    申请号：US11693254

    申请日：2007-03-29

    申请人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Jun Jung Kim ,  Young Gun Ko ,  Jae-Eun Park ,  Haining S. Yang

    IPC分类号： H01L29/76 ,  H01L21/8238

    CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/7843

    摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

    摘要翻译： 提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。 第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。 第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。 第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。 第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

    Pre-silicide spacer removal
    3.
    发明授权
    Pre-silicide spacer removal 失效
    预硅化物间隔物去除

    公开(公告)号：US07504309B2

    公开(公告)日：2009-03-17

    申请号：US11548842

    申请日：2006-10-12

    申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Jun Jung Kim ,  Yaocheng Liu ,  Huilong Zhu

    发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Jun Jung Kim ,  Yaocheng Liu ,  Huilong Zhu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/665 ,  H01L21/32 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.

    摘要翻译： 一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。 在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。 该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。 掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。 在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。 接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

    INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED SPACERS
    4.
    发明申请
    INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED SPACERS 有权
    集成电路系统应用于工程应用的空间

    公开(公告)号：US20080173934A1

    公开(公告)日：2008-07-24

    申请号：US12048994

    申请日：2008-03-14

    申请人： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

    发明人： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

    IPC分类号： H01L27/092

    CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.

    摘要翻译： 一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

    Pre-silicide spacer removal
    5.
    发明申请
    Pre-silicide spacer removal 失效
    预硅化物间隔物去除

    公开(公告)号：US20080090412A1

    公开(公告)日：2008-04-17

    申请号：US11548842

    申请日：2006-10-12

    申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Jun Jung Kim ,  Yaocheng Liu ,  Huilong Zhu

    发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Jun Jung Kim ,  Yaocheng Liu ,  Huilong Zhu

    IPC分类号： H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/32 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.

    摘要翻译： 一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。 在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。 该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。 掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。 在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。 接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

    Dual stress memory technique method and related structure
    6.
    发明授权
    Dual stress memory technique method and related structure 有权
    双应力记忆技术方法及相关结构

    公开(公告)号：US07785950B2

    公开(公告)日：2010-08-31

    申请号：US11164114

    申请日：2005-11-10

    申请人： Sunfei Fang ,  Jun Jung Kim ,  Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Young Way Teh

    发明人： Sunfei Fang ,  Jun Jung Kim ,  Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Young Way Teh

    IPC分类号： H01L21/8238 ,  H01L21/469

    CPC分类号： H01L21/823864 ,  H01L21/823807

    摘要： A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

    摘要翻译： 公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。 该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。 压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。

    Non-conformal stress liner for enhanced MOSFET performance
    7.
    发明授权
    Non-conformal stress liner for enhanced MOSFET performance 失效
    非保形应力衬垫，用于增强MOSFET性能

    公开(公告)号：US07585773B2

    公开(公告)日：2009-09-08

    申请号：US11556591

    申请日：2006-11-03

    申请人： Sunfei Fang ,  Jun Jung Kim ,  Thomas Dyer

    发明人： Sunfei Fang ,  Jun Jung Kim ,  Thomas Dyer

    IPC分类号： H01L29/72

    CPC分类号： H01L21/823807 ,  H01L29/7843

    摘要： A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.

    摘要翻译： 提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。 通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。 本发明是针对制造所述半导体器件的方法。

    NON-CONFORMAL STRESS LINER FOR ENHANCED MOSFET PERFORMANCE
    9.
    发明申请
    NON-CONFORMAL STRESS LINER FOR ENHANCED MOSFET PERFORMANCE 失效
    非稳定应力衬管，用于增强MOSFET性能

    公开(公告)号：US20080122003A1

    公开(公告)日：2008-05-29

    申请号：US11556591

    申请日：2006-11-03

    申请人： Sunfei Fang ,  Jun Jung Kim ,  Thomas Dyer

    发明人： Sunfei Fang ,  Jun Jung Kim ,  Thomas Dyer

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/823807 ,  H01L29/7843

    摘要： A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.

    摘要翻译： 提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。 通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。 本发明是针对制造所述半导体器件的方法。

    Integrated circuit system employing stress-engineered spacers
    10.
    发明授权
    Integrated circuit system employing stress-engineered spacers 有权
    采用应力工程间隔件的集成电路系统

    公开(公告)号：US08338245B2

    公开(公告)日：2012-12-25

    申请号：US12048994

    申请日：2008-03-14

    申请人： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

    发明人： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.

    摘要翻译： 一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。