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公开(公告)号：US20080142897A1
公开(公告)日：2008-06-19
申请号：US11613149
申请日：2006-12-19
申请人： Young Way Teh , Xiangdong Chen , Jamin F. Fen , Jun Jung Kim , Daewon Yang , Roman Knoefler , Michael P. Belyansky
发明人： Young Way Teh , Xiangdong Chen , Jamin F. Fen , Jun Jung Kim , Daewon Yang , Roman Knoefler , Michael P. Belyansky
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.
摘要翻译： 提供了一种集成电路系统，包括在晶片上形成电路元件，在晶片上形成具有不均匀轮廓的应力形成层，并在应力形成层和晶片上形成层间电介质。
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公开(公告)号：US20080044967A1
公开(公告)日：2008-02-21
申请号：US11465799
申请日：2006-08-19
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer on the wafer, protecting a portion of the stress formation layer, and irradiating the wafer for modification of a stress value of an unprotected portion of the stress formation layer.
摘要翻译： 提供一种集成电路系统，包括在晶片上形成电路元件，在晶片上形成应力形成层，保护应力形成层的一部分，以及照射晶片以改变应力的未受保护部分的应力值 形成层。
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公开(公告)号：US06914015B2
公开(公告)日：2005-07-05
申请号：US10605857
申请日：2003-10-31
IPC分类号： H01L21/314 , H01L21/316 , H01L21/318 , H01L21/762 , H01L21/8242 , H01L21/31
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/31608 , H01L21/31625 , H01L21/31629 , H01L21/3185 , H01L21/76224 , H01L27/10844
摘要： An HDP process for high aspect ratio gap filling comprises contacting a semiconductor substrate with an oxide precursor under high density plasma conditions at a first pressure less than about 10 millitorr, wherein said gaps are partially filled with oxide; and further contacting the substrate with an oxide precursor under high density plasma conditions at a second pressure greater than about 10 millitorr, wherein said gaps are further filled with oxide.
摘要翻译： 用于高纵横比间隙填充的HDP工艺包括在高密度等离子体条件下以低于约10毫托的第一压力使半导体衬底与氧化物前体接触，其中所述间隙部分地填充有氧化物; 并且在高密度等离子体条件下，在大于约10毫托的第二压力下进一步使基底与氧化物前体接触，其中所述间隙进一步用氧化物填充。
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公开(公告)号：US08557649B2
公开(公告)日：2013-10-15
申请号：US13278301
申请日：2011-10-21
申请人： Rajasekhar Venigalla , Michael Vincent Aquilino , Massud A. Aminpur , Michael P. Belyansky , Unoh Kwon , Christopher Duncan Sheraw , Daewon Yang
发明人： Rajasekhar Venigalla , Michael Vincent Aquilino , Massud A. Aminpur , Michael P. Belyansky , Unoh Kwon , Christopher Duncan Sheraw , Daewon Yang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/3081 , H01L21/3086 , H01L21/31053 , H01L21/76283
摘要： Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.
摘要翻译： 公开了用于控制半导体结构的高度的方法。 无定形碳被用作控制高度变异性的停止层。 在一个实施例中，控制用于晶体管的替换金属栅极的高度。 在另一个实施例中，控制浅沟槽隔离区的台阶高度。
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公开(公告)号：US20130102125A1
公开(公告)日：2013-04-25
申请号：US13278301
申请日：2011-10-21
申请人： Rajasekhar Venigalla , Michael Vincent Aquilino , Massud A. Aminpur , Michael P. Belyansky , Unoh Kwon , Christopher Duncan Sheraw , Daewon Yang
发明人： Rajasekhar Venigalla , Michael Vincent Aquilino , Massud A. Aminpur , Michael P. Belyansky , Unoh Kwon , Christopher Duncan Sheraw , Daewon Yang
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/3081 , H01L21/3086 , H01L21/31053 , H01L21/76283
摘要： Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.
摘要翻译： 公开了用于控制半导体结构的高度的方法。 无定形碳被用作控制高度变异性的停止层。 在一个实施例中，控制用于晶体管的替换金属栅极的高度。 在另一个实施例中，控制浅沟槽隔离区的台阶高度。
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6.发明申请DIELECTRIC CAP HAVING MATERIAL WITH OPTICAL BAND GAP TO SUBSTANTIALLY BLOCK UV RADIATION DURING CURING TREATMENT, AND RELATED METHODS 审中-公开具有光学带隙的材料的电介质板在固化处理期间实质性地阻挡紫外线辐射，以及相关方法公开(公告)号：US20080173985A1
公开(公告)日：2008-07-24
申请号：US11626552
申请日：2007-01-24
申请人： Michael P. Belyansky , Griselda Bonilla , Xiao Hu Liu , Son Van Nguyen , Thomas M. Shaw , Hosadurga K. Shobha , Daewon Yang
发明人： Michael P. Belyansky , Griselda Bonilla , Xiao Hu Liu , Son Van Nguyen , Thomas M. Shaw , Hosadurga K. Shobha , Daewon Yang
IPC分类号： H01L23/58 , H01L21/318
CPC分类号： H01L21/02123 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/02348 , H01L21/318 , H01L21/3185 , H01L21/76826 , H01L21/76828 , H01L21/76834
摘要： A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability,
摘要翻译： 公开了介电盖和相关方法。 在一个实施例中，电介质盖包括具有光学带隙（例如大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。 电介质盖表现出高模量，并且在ULK UV固化处理后稳定，例如：铜低k后端（BEOL）纳米电子器件，导致更少的膜和器件开裂和改善的可靠性，
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公开(公告)号：US07863646B2
公开(公告)日：2011-01-04
申请号：US11956043
申请日：2007-12-13
IPC分类号： H01L31/111 , H01L21/00
CPC分类号： H01L21/823807 , H01L27/092 , H01L29/7843
摘要： A transistor structure includes a first type of transistor (e.g., P-type) positioned in a first area of the substrate, and a second type of transistor (e.g., N-type) positioned in a second area of the substrate. A first type of stressing layer (compressive conformal nitride) is positioned above the first type of transistor and a second type of stressing layer (compressive tensile nitride) is positioned above the second type of transistor. In addition, another first type of stressing layer (compressive oxide) is positioned above the first type of transistor. Further, another second type of stressing layer (compressive oxide) is positioned above the second type of transistor.
摘要翻译： 晶体管结构包括位于衬底的第一区域中的第一类型的晶体管（例如，P型）和位于衬底的第二区域中的第二类型的晶体管（例如N型）。 第一类型的应力层（压缩共形氮化物）位于第一类型的晶体管上方，并且第二类型的应力层（压缩拉伸氮化物）位于第二类型晶体管之上。 此外，另一种第一类型的应力层（压缩氧化物）位于第一类型的晶体管之上。 此外，另一第二类型的应力层（压缩氧化物）位于第二类型晶体管的上方。
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公开(公告)号：US07569848B2
公开(公告)日：2009-08-04
申请号：US11362773
申请日：2006-02-28
IPC分类号： H01L29/06
CPC分类号： H01L29/0653 , H01L29/66636 , H01L29/7848
摘要： Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.
摘要翻译： 压缩或拉伸材料被选择性地引入到间隔区域的下方并且与半导体衬底的通道区域相邻并且与CMOS电路中的电子和空穴迁移率相关联。 一个过程需要创建虚拟间隔物的步骤，形成介质心轴（即掩模），去除虚拟间隔物，将凹槽蚀刻到下面的半导体衬底中，将压缩或拉伸材料引入每个凹部的一部分中， 每个凹槽与基底材料。
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9.发明授权Field effect transistors with dielectric source drain halo regions and reduced miller capacitance 失效具有介质源极卤素区域的场效应晶体管和减小的磨机电容公开(公告)号：US07342266B2
公开(公告)日：2008-03-11
申请号：US11306710
申请日：2006-01-09
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0653 , H01L29/1083 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/78609 , Y10S438/954
摘要： A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.
摘要翻译： 场效应晶体管（FET）器件包括在半导体衬底的有源器件区域上形成的栅极导体和栅极电介质。 在半导体衬底的有源器件区域中，在栅极导体的一侧上形成漏极区域，并且在栅极导体的相对侧上在半导体衬底的有源器件区域中形成源极区域。 在所述半导体衬底的有源区域中形成介电晕或插塞，所述介电晕或插头设置在所述漏区和体区之间并且在所述源区与所述体区之间接触。
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10.发明授权Oxidation method for altering a film structure and CMOS transistor structure formed therewith 失效用于改变由其形成的膜结构和CMOS晶体管结构的氧化方法公开(公告)号：US06982196B2
公开(公告)日：2006-01-03
申请号：US10605889
申请日：2003-11-04
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译： 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。
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