公开(公告)号：US07308623B2

公开(公告)日：2007-12-11

申请号：US11076020

申请日：2005-03-10

申请人： Richard Slobodnik ,  Paul Stanley Hughes ,  Frank David Frederick ,  Brandon Michael Backlund

发明人： Richard Slobodnik ,  Paul Stanley Hughes ,  Frank David Frederick ,  Brandon Michael Backlund

IPC分类号： G11C29/00

CPC分类号： G11C29/16 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/3602

摘要： An integrated circuit and method for testing memory on that integrated circuit includes processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided for executing test events in order to seek to detect any memory defects in the number of memory units. The controller includes a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the controller is then operable, following the single programming operation, to execute the sequence of test events.

摘要翻译： 用于在该集成电路上测试存储器的集成电路和方法包括可操作以对数据执行数据处理操作的处理逻辑，以及可操作以存储用于由处理逻辑访问的数据的多个存储单元。 还提供了用于执行测试事件的存储器测试控制器，以便寻求检测存储器单元数量中的任何存储器缺陷。 所述控制器包括存储器，用于存储形成要执行的测试事件序列的多个测试事件中的每一个的事件定义信息，以及在单个编程操作期间接收所述多个测试事件中的每一个的事件定义信息的接口 的测试事件，并导致将事件定义为存储在存储器中的信息。 然后，控制器中的事件处理逻辑可以在单个编程操作之后执行测试事件的顺序。

公开(公告)号：US07434119B2

公开(公告)日：2008-10-07

申请号：US11072626

申请日：2005-03-07

申请人： Richard Slobodnik ,  Frank David Frederick

发明人： Richard Slobodnik ,  Frank David Frederick

IPC分类号： G11C29/00

CPC分类号： G11C29/18 ,  G11C2029/1806 ,  G11C2029/3602

摘要： A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.

摘要翻译： 提供了一种存储器自检系统，其包括在自检模式下可操作的自检程序，以生成一系列生成的存储器地址，以执行与具有相关联的存储单元物理访问模式的存储器测试算法相关联的存储器访问操作。 可编程重新映射器可操作以将从自测试指令导出的生成的存储器地址的序列重新映射到重新映射的存储器地址的序列。 可编程重新映射器响应于可编程映射选择数据执行该重映射。 将生成的存储器地址重新映射到重新映射的存储器地址确保在执行存储器自检期间执行的存储器单元访问与相关联的存储器单元物理访问模式一致，而不管存储器阵列的特定实现。

公开(公告)号：US07062689B2

公开(公告)日：2006-06-13

申请号：US10022213

申请日：2001-12-20

申请人： Richard Slobodnik

发明人： Richard Slobodnik

IPC分类号： G11C29/00

CPC分类号： G11C29/16

摘要： A self-test controller for memory devices is provided with an integrated circuit. The self-test controller produces physical memory address values for driving desired memory tests. A mapping circuit serves to map these physical memory address signals to logical memory address signals as required by the particular memory devices. In this way a generic self-test controller may be provided that is able to drive tests within multiple different memory devices by providing a relatively simple mapping circuit.

摘要翻译： 用于存储器件的自检控制器具有集成电路。 自检控制器产生用于驱动所需内存测试的物理内存地址值。 映射电路用于将这些物理存储器地址信号映射到特定存储器件所要求的逻辑存储器地址信号。 以这种方式，可以提供通用的自检控制器，其能够通过提供相对简单的映射电路来驱动多个不同存储器件内的测试。

公开(公告)号：US07293212B2

公开(公告)日：2007-11-06

申请号：US11085599

申请日：2005-03-22

申请人： Conrado Blasco Allue ,  Stephen John Hill ,  Richard Slobodnik

发明人： Conrado Blasco Allue ,  Stephen John Hill ,  Richard Slobodnik

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/16 ,  G01R31/31705 ,  G01R31/31722 ,  G01R31/31723 ,  G11C29/08 ,  G11C2029/0401

摘要： A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units. In the operational mode a configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units whereas a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. The first ring sequence is identical to the second ring sequence and the data processing apparatus is operable in the self-test mode to couple the configuration ring-bus and the debug ring-bus to provide a combined data path for communication of self-test data between the plurality of functional units.

摘要翻译： 数据处理装置可以在自检模式或操作模式中操作。 所述设备包括多个功能单元，所述功能单元中的至少一个可操作以执行数据处理操作，并且所述多个功能单元的至少一个子集具有用于存储配置数据的相应协处理器寄存器中的至少一个， 用于存储调试数据的相应调试寄存器和相应的功能单元存储器。 一种存储器自检控制器，其可在自检模式下操作以输出用于执行存取操作的自检数据，以确认功能单元存储器的正确操作。 调试控制器输出调试数据并协调调试操作，调试控制器是多个功能单元之一。 在操作模式中，配置环总线提供用于在多个功能单元的第一环序列之间通信配置指令的环路，而调试环总线提供用于在第二环序列之间通信调试数据的环路 的多个功能单元。 第一环序列与第二环序列相同，数据处理装置在自检模式下可操作以耦合配置环总线和调试环总线，以提供用于通信自检数据的组合数据路径 在多个功能单元之间。

公开(公告)号：US07269766B2

公开(公告)日：2007-09-11

申请号：US10025816

申请日：2001-12-26

申请人： Richard Slobodnik ,  Stephen John Hill ,  Gerard Richard Williams

发明人： Richard Slobodnik ,  Stephen John Hill ,  Gerard Richard Williams

IPC分类号： G11C29/00

CPC分类号： G11C29/16

摘要： A self-test controller 10 is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test instruction. Combining multiple such self-test instructions allows a custom test methodology to be built up by a user using a generic self-test controller 10.

摘要翻译： 自测试控制器10响应于在自检指令中扫描以执行测试操作，包括生成由自检指令指定的存储器地址序列。 组合多个这样的自检指令允许由用户使用通用自检控制器10构建自定义测试方法。

公开(公告)号：US20060200713A1

公开(公告)日：2006-09-07

申请号：US11072626

申请日：2005-03-07

申请人： Richard Slobodnik ,  Frank Frederick

发明人： Richard Slobodnik ,  Frank Frederick

IPC分类号： G11C29/00

CPC分类号： G11C29/18 ,  G11C2029/1806 ,  G11C2029/3602

摘要： A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.

摘要翻译： 提供了一种存储器自检系统，其包括在自检模式下可操作的自检程序，以生成一系列生成的存储器地址，以执行与具有相关联的存储单元物理访问模式的存储器测试算法相关联的存储器访问操作。 可编程重新映射器可操作以将从自测试指令导出的生成的存储器地址的序列重新映射到重新映射的存储器地址的序列。 可编程重新映射器响应于可编程映射选择数据执行该重映射。 将生成的存储器地址重新映射到重新映射的存储器地址确保在执行存储器自检期间执行的存储器单元访问与相关联的存储器单元物理访问模式一致，而不管存储器阵列的特定实现。

公开(公告)号：US07053675B2

公开(公告)日：2006-05-30

申请号：US10626871

申请日：2003-07-25

申请人： Richard Slobodnik ,  Gerard Richard Williams ,  Mark Allen Silla

发明人： Richard Slobodnik ,  Gerard Richard Williams ,  Mark Allen Silla

IPC分类号： G06F1/04

CPC分类号： G06F1/08

摘要： A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way. The processor clock control device comprises: at least two clock signal inputs each operable to receive a clock signal, said clock signals comprising a first and a second clock signal; a sensor operable to sense said first and said second clock signals; a clock signal output operable to output a clock signal for input to a processor; and a clock switching signal input for receiving a switching signal operable to control switching of said clock signal output from said first clock signal to said second clock signal; wherein said processor clock control device is operable on receipt of said clock switching signal to sense said first clock signal and when said first clock signal transitions from a first predetermined level to a second level, said processor clock control device is operable to hold said clock signal output at said second level, and then to sense said second clock signal and when said second clock signal transitions from said second level to said first predetermined level to output said second clock signal.

摘要翻译： 公开了一种处理器时钟控制装置，其可操作以控制以无毛刺方式输入到处理器的时钟信号之间的切换。 处理器时钟控制装置包括：至少两个时钟信号输入，每个可操作以接收时钟信号，所述时钟信号包括第一和第二时钟信号; 传感器，其可操作以感测所述第一和所述第二时钟信号; 时钟信号输出，其可操作以输出用于输入到处理器的时钟信号; 以及时钟切换信号输入，用于接收可操作以控制从所述第一时钟信号输出到所述第二时钟信号的所述时钟信号的切换的切换信号; 其中所述处理器时钟控制装置在接收到所述时钟切换信号以操作所述第一时钟信号时可操作，并且当所述第一时钟信号从第一预定电平转变到第二电平时，所述处理器时钟控制装置可操作以保持所述时钟信号 在所述第二电平输出，然后感测所述第二时钟信号，并且当所述第二时钟信号从所述第二电平转换到所述第一预定电平时，输出所述第二时钟信号。

公开(公告)号：US20060218449A1

公开(公告)日：2006-09-28

申请号：US11085599

申请日：2005-03-22

申请人： Conrado Blasco Allue ,  Stephen Hill ,  Richard Slobodnik

发明人： Conrado Blasco Allue ,  Stephen Hill ,  Richard Slobodnik

IPC分类号： G06F11/00

CPC分类号： G11C29/16 ,  G01R31/31705 ,  G01R31/31722 ,  G01R31/31723 ,  G11C29/08 ,  G11C2029/0401

摘要： A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units. In the operational mode a configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units whereas a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. The first ring sequence is identical to the second ring sequence and the data processing apparatus is operable in the self-test mode to couple the configuration ring-bus and the debug ring-bus to provide a combined data path for communication of self-test data between the plurality of functional units.

摘要翻译： 数据处理装置可以在自检模式或操作模式中操作。 所述设备包括多个功能单元，所述功能单元中的至少一个可操作以执行数据处理操作，并且所述多个功能单元的至少一个子集具有用于存储配置数据的相应协处理器寄存器中的至少一个， 用于存储调试数据的相应调试寄存器和相应的功能单元存储器。 一种存储器自检控制器，其可在自检模式下操作以输出用于执行存取操作的自检数据，以确认功能单元存储器的正确操作。 调试控制器输出调试数据并协调调试操作，调试控制器是多个功能单元之一。 在操作模式中，配置环总线提供用于在多个功能单元的第一环序列之间通信配置指令的环路，而调试环总线提供用于在第二环序列之间通信调试数据的环路 的多个功能单元。 第一环序列与第二环序列相同，数据处理装置在自检模式下可操作以耦合配置环总线和调试环总线，以提供用于通信自检数据的组合数据路径 在多个功能单元之间。

公开(公告)号：US20060212764A1

公开(公告)日：2006-09-21

申请号：US11076020

申请日：2005-03-10

申请人： Richard Slobodnik ,  Paul Hughes ,  Frank Frederick ,  Brandon Backlund

发明人： Richard Slobodnik ,  Paul Hughes ,  Frank Frederick ,  Brandon Backlund

IPC分类号： G11C29/00

CPC分类号： G11C29/16 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/3602

摘要： An integrated circuit and method for testing memory on that integrated circuit are provided. The integrated circuit comprises processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided which is operable to execute test events in order to seek to detect any memory defects in the number of memory units. The memory test controller comprises a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the memory test controller is then operable, following the single programming operation, to execute the sequence of test events. This provides an efficient technique for enabling a sequence of test events to be programmed at run time.

摘要翻译： 提供了一种用于测试该集成电路上的存储器的集成电路和方法。 集成电路包括可操作以对数据执行数据处理操作的处理逻辑，以及可操作以存储用于由处理逻辑进行访问的数据的多个存储单元。 还提供了一种存储器测试控制器，其可操作以执行测试事件，以便寻求检测存储器单元数量中的任何存储器缺陷。 存储器测试控制器包括可操作以存储形成要执行的测试事件序列的多个测试事件中的每一个的事件定义信息的存储器，以及在单个编程操作期间接收每个测试事件的事件定义信息的接口 所述多个测试事件并且使所述事件定义要存储在所述存储器中的信息。 然后，在单个编程操作之后，存储器测试控制器内的事件处理逻辑可以执行测试事件的顺序。 这提供了一种有效的技术，可以在运行时对一系列测试事件进行编程。

公开(公告)号：US20050017763A1

公开(公告)日：2005-01-27

申请号：US10626871

申请日：2003-07-25

申请人： Richard Slobodnik ,  Gerard Williams ,  Mark Silla

发明人： Richard Slobodnik ,  Gerard Williams ,  Mark Silla

IPC分类号： G06F1/08 ,  H03K3/00

CPC分类号： G06F1/08

摘要： A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way. The processor clock control device comprises: at least two clock signal inputs each operable to receive a clock signal, said clock signals comprising a first and a second clock signal; a sensor operable to sense said first and said second clock signals; a clock signal output operable to output a clock signal for input to a processor; and a clock switching signal input for receiving a switching signal operable to control switching of said clock signal output from said first clock signal to said second clock signal; wherein said processor clock control device is operable on receipt of said clock switching signal to sense said first clock signal and when said first clock signal transitions from a first predetermined level to a second level, said processor clock control device is operable to hold said clock signal output at said second level, and then to sense said second clock signal and when said second clock signal transitions from said second level to said first predetermined level to output said second clock signal.

摘要翻译： 公开了一种处理器时钟控制装置，其可操作以控制以无毛刺方式输入到处理器的时钟信号之间的切换。 处理器时钟控制装置包括：至少两个时钟信号输入，每个可操作以接收时钟信号，所述时钟信号包括第一和第二时钟信号; 传感器，其可操作以感测所述第一和所述第二时钟信号; 时钟信号输出，其可操作以输出用于输入到处理器的时钟信号; 以及时钟切换信号输入，用于接收可操作以控制从所述第一时钟信号输出到所述第二时钟信号的所述时钟信号的切换的切换信号; 其中所述处理器时钟控制装置在接收到所述时钟切换信号以操作所述第一时钟信号时可操作，并且当所述第一时钟信号从第一预定电平转变到第二电平时，所述处理器时钟控制装置可操作以保持所述时钟信号 在所述第二电平输出，然后感测所述第二时钟信号，并且当所述第二时钟信号从所述第二电平转换到所述第一预定电平时，输出所述第二时钟信号。