公开(公告)号：US20060200713A1

公开(公告)日：2006-09-07

申请号：US11072626

申请日：2005-03-07

申请人： Richard Slobodnik ,  Frank Frederick

发明人： Richard Slobodnik ,  Frank Frederick

IPC分类号： G11C29/00

CPC分类号： G11C29/18 ,  G11C2029/1806 ,  G11C2029/3602

摘要： A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.

摘要翻译： 提供了一种存储器自检系统，其包括在自检模式下可操作的自检程序，以生成一系列生成的存储器地址，以执行与具有相关联的存储单元物理访问模式的存储器测试算法相关联的存储器访问操作。 可编程重新映射器可操作以将从自测试指令导出的生成的存储器地址的序列重新映射到重新映射的存储器地址的序列。 可编程重新映射器响应于可编程映射选择数据执行该重映射。 将生成的存储器地址重新映射到重新映射的存储器地址确保在执行存储器自检期间执行的存储器单元访问与相关联的存储器单元物理访问模式一致，而不管存储器阵列的特定实现。

公开(公告)号：US20060212764A1

公开(公告)日：2006-09-21

申请号：US11076020

申请日：2005-03-10

申请人： Richard Slobodnik ,  Paul Hughes ,  Frank Frederick ,  Brandon Backlund

发明人： Richard Slobodnik ,  Paul Hughes ,  Frank Frederick ,  Brandon Backlund

IPC分类号： G11C29/00

CPC分类号： G11C29/16 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/3602

摘要： An integrated circuit and method for testing memory on that integrated circuit are provided. The integrated circuit comprises processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided which is operable to execute test events in order to seek to detect any memory defects in the number of memory units. The memory test controller comprises a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the memory test controller is then operable, following the single programming operation, to execute the sequence of test events. This provides an efficient technique for enabling a sequence of test events to be programmed at run time.

摘要翻译： 提供了一种用于测试该集成电路上的存储器的集成电路和方法。 集成电路包括可操作以对数据执行数据处理操作的处理逻辑，以及可操作以存储用于由处理逻辑进行访问的数据的多个存储单元。 还提供了一种存储器测试控制器，其可操作以执行测试事件，以便寻求检测存储器单元数量中的任何存储器缺陷。 存储器测试控制器包括可操作以存储形成要执行的测试事件序列的多个测试事件中的每一个的事件定义信息的存储器，以及在单个编程操作期间接收每个测试事件的事件定义信息的接口 所述多个测试事件并且使所述事件定义要存储在所述存储器中的信息。 然后，在单个编程操作之后，存储器测试控制器内的事件处理逻辑可以执行测试事件的顺序。 这提供了一种有效的技术，可以在运行时对一系列测试事件进行编程。

公开(公告)号：US20070265131A1

公开(公告)日：2007-11-15

申请号：US11382732

申请日：2006-05-11

申请人： Anthony Pistagnesi ,  Frank Frederick ,  Jeffrey Japinga ,  Shawn Bronner

发明人： Anthony Pistagnesi ,  Frank Frederick ,  Jeffrey Japinga ,  Shawn Bronner

IPC分类号： F16H48/06

CPC分类号： B60K17/20 ,  F16H48/08 ,  F16H48/26 ,  F16H48/30 ,  F16H48/32 ,  F16H48/34 ,  F16H48/40 ,  F16H2048/204 ,  F16H2048/346 ,  F16H2200/2071

摘要： An active torque biasing differential includes a housing and an outer annulus disposed within the housing. An inner annulus is contained within the outer annulus. The inner annulus includes a plurality of slots. A plurality of vanes are disposed in the slots in the inner annulus. The vanes slidably contact the outer annulus. The vanes include a plurality of orifices formed therein. An electromagnetic coil is placed to apply a magnetic field to a chamber bounded by the outer annulus and inner annulus.

摘要翻译： 主动扭矩偏置差速器包括壳体和设置在壳体内的外环。 内环形内包含在外环内。 内环包括多个槽。 多个叶片设置在内环的槽中。 叶片滑动接触外环。 叶片包括形成在其中的多个孔。 放置电磁线圈以将磁场施加到由外环和内环限定的室。

公开(公告)号：US20060242449A1

公开(公告)日：2006-10-26

申请号：US11114240

申请日：2005-04-26

申请人： Frank Frederick

发明人： Frank Frederick

IPC分类号： G06F1/04

CPC分类号： G01R31/31727

摘要： A processor clock control device operable to control a plurality of clock signals output to a processor,- said processor comprising a plurality of domains each clocked by a respective one of said plurality of clock signals, said processor being operable in different modes including a functional mode and a test mode, said processor clock control device comprising: a clock signal input operable to receive a slower reference clock signal or a higher speed operational clock signal; at least two clock signal outputs each operable to output a clock signal to a respective domain of said processor; a mode control signal input operable to receive a mode control signal indicating a mode of operation of said processor; a launch control signal input operable to receive a launch control signal, said launch control signal indicating portions of said processor to be tested; and an initiation signal input operable to receive an initiation signal indicating initiation of a processor test; wherein said processor clock control device is operable: in response to receipt of a test mode signal at said mode control signal input to receive a reference clock at said clock signal input and to output said reference clock at at least one of said plurality of clock signal outputs; and in response to a predetermined launch control signal received at said launch control signal input, said predetermined launch control signal indicating testing of a path between one of said clocked domains clocked by one of said clock signal outputs and one other of said clocked domains clocked by one other of said clock signal outputs, and following receipt of said initiation signal, to independently control said plurality of clock signal outputs such that at least one launch clock pulse is output from said one of said clock signal outputs while said one other of said clock signal outputs is suppressed, and following this to output at least one capture clock pulse from said one other of said clock signal outputs while said one of said plurality of clock signal outputs is suppressed.

公开(公告)号：US20050222809A1

公开(公告)日：2005-10-06

申请号：US10812309

申请日：2004-03-30

申请人： Teresa McLaurin ,  Frank Frederick

发明人： Teresa McLaurin ,  Frank Frederick

IPC分类号： G06F11/267 ,  G06F11/30

CPC分类号： G06F11/267 ,  G01R31/31717 ,  G11C29/02 ,  G11C29/022 ,  G11C2029/3202

摘要： In order to test the memory access signal connections between a data processing circuit, such as a processor core 2, and a memory 4, a subset of memory access signal connections 8 are provided with associated scan chain cells 10 so that they may be directly tested. The remainder memory access signal connections 12 which are common to all the expected configurations of the memory 4 are tested by being driven by the processor core 2 itself with data being passed through the memory and captured back within the processor core 2 for checking.

摘要翻译： 为了测试数据处理电路（例如处理器核心2）和存储器4之间的存储器访问信号连接，存储器访问信号连接8的子集被提供有相关联的扫描链单元10，使得它们可以被直接测试 。 存储器4的所有预期配置共同的剩余存储器访问信号连接12被处理器核心2本身驱动，数据被传送通过存储器并被捕获回到处理器核心2中进行检查。

公开(公告)号：US20050225126A1

公开(公告)日：2005-10-13

申请号：US10822918

申请日：2004-04-13

申请人： Frank Frederick

发明人： Frank Frederick

IPC分类号： A45F3/04 ,  A47C1/00 ,  A47C4/52 ,  A47C9/00 ,  A47C9/10

CPC分类号： A47C15/004 ,  A45F3/04 ,  A47C4/52

摘要： A packable seating apparatus having a single planar surface with a seat attached thereto, wherein the lower portion of the planar surface forms legs which raise the seat portion from the ground. The apparatus has storage compartments formed therein, support for a sleeping bag, and a color change device. The apparatus further utilizes any convenient surface, such as a tree or the like, as an additional support. In an alternate embodiment, the present invention includes a kickstand to allow free-standing support.

摘要翻译： 一种具有单个平面的可包装座椅装置，其中安装有座椅，其中平面表面的下部形成将座椅部分从地面上升的腿部。 该装置具有形成在其中的储存室，用于睡袋的支撑件和变色装置。 该装置进一步利用任何方便的表面，例如树等作为附加的支撑。 在一个替代实施例中，本发明包括支撑架以允许独立的支撑。

公开(公告)号：US06877123B2

公开(公告)日：2005-04-05

申请号：US10025291

申请日：2001-12-19

申请人： Thomas K. Johnston ,  Frank Frederick

发明人： Thomas K. Johnston ,  Frank Frederick

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318552 ,  G01R31/31727

摘要： Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.

摘要翻译： 本发明的实施例一般涉及扫描时钟波形生成。 一个实施例使用全局和局部圆形移位寄存器来提供针对测试器的可管理频率的一系列移位/捕获脉冲和相移的启动脉冲，以便提供高速测试。 因此，与待测集成电路的正常工作频率相比，扫描测试图案可以以更低的频率移入或移出状态元件，同时仍允许进行高速测试。 替代实施例利用与静态存储设备和波形发生器组合的循环移位寄存器来提供移位/捕获脉冲和启动脉冲。 本发明的实施例还允许时钟反转，其中时钟和时钟条信号在正常模式期间是依赖的，并且在扫描测试模式期间是独立的。