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公开(公告)号：US20110221502A1
公开(公告)日：2011-09-15
申请号：US13129107
申请日：2009-11-10
IPC分类号： H03L5/00
CPC分类号： G01R31/318508
摘要： Disclosed is an integrated circuit (200) comprising a plurality of cores (110, 110), at least some of the cores being located in different power domains (VDD1, VDD2), each core being surrounded by a test wrapper (220) comprising a plurality of wrapper cells (128, 230), wherein each of said test wrappers are located in a single power domain (VDD3) and each plurality of wrapper cells comprises wrapper output cells (230) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter (232, 240) for shifting the voltage of said signal to the voltage of the single power domain (VDD3). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.
摘要翻译： 公开了一种包括多个核心（110,110）的集成电路（200），至少一些核心位于不同的电力域（VDD1，VDD2）中，每个核心被测试包装（220）包围，包括 多个封装单元（128,230），其中每个所述测试封装器位于单个功率域（VDD3）中，并且每个多个封装单元包括封装输出单元（230），每个封装器单元布置成从其相关联的核输出信号， 每个所述包装器输出单元包括用于将所述信号的电压移动到单个电源域（VDD3）的电压的输出电平移位器（232,240）。 还公开了用于测试这种IC和用于设计这种IC的标准库单元的方法。
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公开(公告)号：US08531204B2
公开(公告)日：2013-09-10
申请号：US13129107
申请日：2009-11-10
IPC分类号： H03K19/00 , H03K19/0175 , H03L5/00
CPC分类号： G01R31/318508
摘要： Disclosed is an integrated circuit (200) comprising a plurality of cores (110, 110), at least some of the cores being located in different power domains (VDD1, VDD2), each core being surrounded by a test wrapper (220) comprising a plurality of wrapper cells (128, 230), wherein each of said test wrappers are located in a single power domain (VDD3) and each plurality of wrapper cells comprises wrapper output cells (230) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter (232, 240) for shifting the voltage of said signal to the voltage of the single power domain (VDD3). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.
摘要翻译： 公开了一种包括多个核心（110,110）的集成电路（200），至少一些核心位于不同的电力域（VDD1，VDD2）中，每个核心被测试包装（220）包围，包括 多个封装单元（128,230），其中每个所述测试封装器位于单个功率域（VDD3）中，并且每个多个封装单元包括封装输出单元（230），每个封装器单元布置成从其相关联的核输出信号， 每个所述包装器输出单元包括用于将所述信号的电压移动到单个电源域（VDD3）的电压的输出电平移位器（232,240）。 还公开了用于测试这种IC和用于设计这种IC的标准库单元的方法。
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公开(公告)号：US20080106327A1
公开(公告)日：2008-05-08
申请号：US11629716
申请日：2005-06-09
IPC分类号： G05F3/02
CPC分类号： G06F1/3203 , G06F1/28 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： The present invention relates to a method and circuit arrangement for controlling performance of an integrated circuit in response to a monitored performance indicator, wherein power supply of the integrated circuit is controlled based on said performance indicator. At least one of a noise level of the controlled power supply and a clock frequency generated in said integrated circuit is monitored and a respective control signal is fed back to the controlling function if the checking result is not within a predetermined range. Thereby, an simple and easily extendable automatic adaptation to process variations can be achieved.
摘要翻译： 本发明涉及一种用于响应于监视的性能指示器来控制集成电路的性能的方法和电路装置，其中基于所述性能指标来控制集成电路的电源。 如果检查结果不在预定范围内，则监视受控电源的噪声电平和在所述集成电路中产生的时钟频率中的至少一个并将相应的控制信号反馈给控制功能。 因此，可以实现简单且易于扩展的自动适应过程变化。
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公开(公告)号：US20080195878A1
公开(公告)日：2008-08-14
申请号：US11629718
申请日：2005-06-07
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： The present invention relates to a control system and method of controlling at least one performance parameter of an integrated circuit. The at least performance parameter is controlled based on a control word. However, the signaled control information is reduced to a binary control signal simply instructing increase or decrease of said at least one performance parameter. This is achieved by modifying the control word in accordance with the binary control signal, e.g., by using the binary control signal to define a binary value shifted into a shift register means (31). Thereby, a fast and simple control functionality can be provided, which does not require any further hardware to adjust the performance parameter.
摘要翻译： 本发明涉及控制集成电路的至少一个性能参数的控制系统和方法。 基于控制字来控制至少性能参数。 然而，信号控制信息被简化为仅指示增加或减少所述至少一个性能参数的二进制控制信号。 这通过例如通过使用二进制控制信号来限定被移入移位寄存器装置（31）的二进制值来根据二进制控制信号修改控制字来实现。 因此，可以提供快速和简单的控制功能，其不需要任何进一步的硬件来调整性能参数。
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公开(公告)号：US07102254B2
公开(公告)日：2006-09-05
申请号：US10502183
申请日：2002-12-18
申请人： Hendricus Joseph Maria Veendrick , Rinze Ida Mechtildis Peter Meijer , Kiran Batni Raghavendra Rao
发明人： Hendricus Joseph Maria Veendrick , Rinze Ida Mechtildis Peter Meijer , Kiran Batni Raghavendra Rao
IPC分类号： H01H35/00
CPC分类号： H03K19/0016 , Y10T307/832
摘要： An integrated circuit (100) has a circuit portion (102) that can be switched to a standby mode through an enable transistor (104), which is coupled between an internal power supply line (120) and an external power supply line (130). The enable transistor (104) is controlled by control circuitry via a control line (160). The control line (160) is coupled to the gates of a first transistor (152) and a further transistor (154) of a logic gate (150). The substrate of the further transistor (154) is coupled to a backbias generator (170). Consequently, when the enable transistor (104) is switched off, the further transistor (154) is enabled and applies a substantial backbias to the gate of the enable transistor (104), thus dramatically reducing the leakage current from the circuit portion (102) through the enable transistor (104).
摘要翻译： 集成电路（100）具有电路部分（102），其可以通过耦合在内部电源线（120）和外部电源线（130）之间的使能晶体管（104）切换到待机模式， 。 使能晶体管（104）由控制电路经由控制线（160）控制。 控制线（160）耦合到逻辑门（150）的第一晶体管（152）和另一晶体管（154）的栅极。 另一个晶体管（154）的衬底耦合到回流发生器（170）。 因此，当使能晶体管（104）关断时，另外的晶体管（154）被使能并且向使能晶体管（104）的栅极施加实质的反向比，从而显着地减少来自电路部分（102）的漏电流， 通过使能晶体管（104）。
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公开(公告)号：US08497605B2
公开(公告)日：2013-07-30
申请号：US12891482
申请日：2010-09-27
IPC分类号： G05F3/06
CPC分类号： H02M3/158 , G06F1/3203 , G06F1/325 , G06F1/3287 , Y02D10/171 , Y10T307/391 , Y10T307/702
摘要： A power supply arrangement is for supplying power to a chip core. A dc-dc converter arrangement is used both for a wake-up state of the core in preparation for an active state, and for a shut down charge recycling state in which the core supplies charge to the dc-dc converter. Thus, the dc-dc converter arrangement functions both to control powering on of the core in an efficient manner and the powering down of the core to implement charge recycling. In an active state, the core is supplied with power from the high power supply line.
摘要翻译： 电源装置用于向芯片芯供电。 一个dc-dc转换器装置用于核心的唤醒状态以准备有效状态，以及关闭电荷再循环状态，其中核心向dc-dc转换器提供电荷。 因此，dc-dc转换器装置既能有效地控制核心的上电，也可以起到核心的电源以实现电荷回收。 在激活状态下，核心由高电源线供电。
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公开(公告)号：US08302059B2
公开(公告)日：2012-10-30
申请号：US12994508
申请日：2009-05-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing a power switch block (200) for an integrated circuit layout in a predefined integrated circuit technology is disclosed. The power switch block (200) includes a segment (710) comprising a plurality of spaced parallel conductors (110, 120, 130, 140) each having a predefined height in said technology, a stack of a first power switch (115) of a first conductivity type and a pair of drivers (152; 154) for respectively driving the first power switch (115) and a second power switch (135), said drivers having predefined dimensions in said technology, and the second switch (135) of a second conductivity type. The method comprises providing respective predefined width/length ratios for said power switches (115; 135); determining a total height of the segment (710) from the sum of the predefined heights of the individual conductors (110; 120; 130; 140) and respective spacings (310; 320) between said individual conductors, determining the height of the first transistor (115) from the difference between the total height and the predefined driver height; determining the width of the first transistor (115) from the combined predefined widths of the pair of drivers (152; 154); optimizing the first power switch layout within its determined height and width based on its predefined width/length ratio; and optimizing the second power switch layout based on its predefined width/height ratio.
摘要翻译： 公开了一种在预定义的集成电路技术中设计用于集成电路布局的功率开关块（200）的方法。 功率开关块（200）包括一个段（710），其包括多个间隔开的平行导体（110,120,130,140），每个导体在所述技术中具有预定高度，第一电源开关（115） 第一导电类型和用于分别驱动第一电力开关（115）和第二电力开关（135）的一对驱动器（152; 154），所述驱动器在所述技术中具有预定尺寸，并且第二开关（135） 第二导电类型。 该方法包括为所述功率开关（115; 135）提供相应的预定宽度/长度比; 从各个导体（110; 120; 130; 140）的预定高度和各个导体之间的相应间隔（310; 320）的总和确定段（710）的总高度，确定第一晶体管 （115）从总高度和预定义的驾驶员高度之间的差异; 从所述一对驱动器（152; 154）的组合的预定宽度确定所述第一晶体管（115）的宽度; 基于其预定的宽度/长度比，在其确定的高度和宽度内优化第一功率开关布局; 并基于其预定义的宽/高比优化第二功率开关布局。
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公开(公告)号：US07741866B2
公开(公告)日：2010-06-22
申请号：US10583808
申请日：2004-12-08
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/018585
摘要： The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the drive capacity of the circuit component is adjusted responsive to the determination result. In particular, the circuit component is tailored to have just sufficient drive capacity depending on the potential load which may be determined by examining a configuration information loaded to the circuit arrangement. Tailoring for sufficient drive can be achieved either by varying the size or number of circuit components or by adjusting the threshold voltage of circuit elements, or by doing both. Thereby, power consumption can be reduced when circuit components are driven at loads lower than the worst case load.
摘要翻译： 本发明涉及一种控制电路装置功率消耗的电路装置和方法，其中，确定在电路部件处施加的负载，并根据确定结果来调节电路部件的驱动能力。 特别地，根据可以通过检查加载到电路装置的配置信息来确定的潜在负载，电路部件被调整为具有足够的驱动能力。 可以通过改变电路部件的尺寸或数量或通过调节电路元件的阈值电压，或通过两者来实现足够的驱动的裁缝。 因此，当电流元件在比最坏情况负载低的负载下驱动时，能够降低功耗。
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公开(公告)号：US08120410B2
公开(公告)日：2012-02-21
申请号：US11629768
申请日：2005-06-09
IPC分类号： G05F1/10
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally controlled so as to individually adjust power supply for each of said at least two electrically isolated circuit regions (10) based on the at least one monitored working parameter. Thereby, a fast and simple control functionality with low area overhead can be provided.
摘要翻译： 本发明涉及一种用于控制集成电路中的电源的电路装置和方法，其中监控至少一个电隔离电路区域（10）的至少一个工作参数，并且可变电阻器装置的电导率被局部控制 用于基于所述至少一个被监视的工作参数单独地调节所述至少两个电隔离电路区域（10）中的每一个的电源。 因此，可以提供具有低面积开销的快速且简单的控制功能。
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公开(公告)号：US07930577B2
公开(公告)日：2011-04-19
申请号：US11629716
申请日：2005-06-09
IPC分类号： G06F1/28
CPC分类号： G06F1/3203 , G06F1/28 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： The present invention relates to a method and circuit arrangement for controlling performance of an integrated circuit in response to a monitored performance indicator, wherein power supply of the integrated circuit is controlled based on said performance indicator. At least one of a noise level of the controlled power supply and a clock frequency generated in said integrated circuit is monitored and a respective control signal is fed back to the controlling function if the checking result is not within a predetermined range. Thereby, an simple and easily extendable automatic adaptation to process variations can be achieved.
摘要翻译： 本发明涉及一种用于响应于监视的性能指示器来控制集成电路的性能的方法和电路装置，其中基于所述性能指标来控制集成电路的电源。 如果检查结果不在预定范围内，则监视受控电源的噪声电平和在所述集成电路中产生的时钟频率中的至少一个并将相应的控制信号反馈给控制功能。 因此，可以实现简单且易于扩展的自动适应过程变化。
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