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    Controllable delay circuit for delaying an electrical signal
    3.
    发明授权
    Controllable delay circuit for delaying an electrical signal 有权
    用于延迟电信号的可控延迟电路

    公开(公告)号：US06914468B2

    公开(公告)日：2005-07-05

    申请号：US10479552

    申请日：2002-06-04

    申请人： Victor Emmanuel Stephanus Van Dijk ,  Rinze Ida Mechtildis Peter Meijer ,  Hendricus Joseph Maria Veendrick

    发明人： Victor Emmanuel Stephanus Van Dijk ,  Rinze Ida Mechtildis Peter Meijer ,  Hendricus Joseph Maria Veendrick

    IPC分类号： H03K5/13 ,  H03K5/15 ,  H03H11/26

    CPC分类号： H03K5/131 ,  H03K5/15013

    摘要： The invention relates to a controllable delay circuit for delaying an electrical input signal wherein the controllable delay circuit is arranged for receiving an input signal and at least one control signal, wherein, in use, the delay circuit delays the input signal by a delay for generating an output signal, wherein the delay is a function of the at least one control signal, wherein the delay circuit comprises a first module for generating a base signal and at least one support signal on the basis of the input signal and the at least one control signal, wherein, in use, the phase and/or the amplitude of the at least one support signal is controllable with respect to the phase and/or the amplitude of the base-signal by means of the at least one control signal, wherein the delay circuit also comprises a second module connected to the first module, which second module comprises a signal-conductor and at least one support conductor, wherein the signal conductor and the at least one support conductor extend, at least over a part of the conductors, essentially parallel to one another in one another's vicinity, wherein, in use, the first module supplies the base signal to a first end of the signal conductor for generating an output-signal at a second end of the signal conductor, and wherein, in use, the first module supplies the at least one support signal to the at least one support conductor.

    摘要翻译： 本发明涉及一种用于延迟电输入信号的可控延迟电路，其中可控延迟电路用于接收输入信号和至少一个控制信号，其中在使用中延迟电路延迟输入信号延迟以产生 输出信号，其中所述延迟是所述至少一个控制信号的函数，其中所述延迟电路包括用于基于所述输入信号和所述至少一个控制器产生基本信号和至少一个支持信号的第一模块 信号，其中在使用中，所述至少一个支持信号的相位和/或振幅可通过所述至少一个控制信号相对于所述基本信号的相位和/或振幅来控制，其中， 延迟电路还包括连接到第一模块的第二模块，该第二模块包括信号导体和至少一个支撑导体，其中信号导线和至少一个支撑 t导体至少在导体的一部分上延伸，在彼此的附近基本上彼此平行，其中在使用中，第一模块将基本信号提供给信号导体的第一端，用于产生输出信号 信号导体的第二端，并且其中在使用中，所述第一模块将所述至少一个支撑信号提供给所述至少一个支撑导体。

    DLL FOR PERIOD JITTER MEASUREMENT
    5.
    发明申请
    DLL FOR PERIOD JITTER MEASUREMENT 有权
    DLL用于定期测试

    公开(公告)号：US20110128055A1

    公开(公告)日：2011-06-02

    申请号：US12995153

    申请日：2009-05-27

    申请人： Marcel J.M. Pelgrom ,  Hendricus Joseph Maria Veendrick ,  Victor Zieren

    发明人： Marcel J.M. Pelgrom ,  Hendricus Joseph Maria Veendrick ,  Victor Zieren

    IPC分类号： H03L7/08

    CPC分类号： G01R31/31709

    摘要： A sensor (400) for sensing jitter in a clock signal has a DLL (402, 310, 312) for locking a clock signal and a delayed version of the clock signal. The sensor comprises a delay line (402) having a first number of cascaded controllable delay segments. The DLL uses a second number of the cascaded delay segments for generating a delay of an average clock period of the clock signal. The second number is smaller than the first number. The sensor also has a comparator (408) for supplying a sensor output signal representative of a comparison of the clock signal and a further delayed version of the clock signal. The further delayed version of the clock signal is obtained from an output of a specific one of the delay segments located in the delay line after the second number of cascaded delay segments.

    摘要翻译： 用于感测时钟信号中的抖动的传感器（400）具有用于锁定时钟信号和时钟信号的延迟版本的DLL（402,310,312）。 传感器包括具有第一数量级联的可控延迟段的延迟线（402）。 DLL使用第二数量的级联延迟段来产生时钟信号的平均时钟周期的延迟。 第二个数字小于第一个数字。 传感器还具有比较器（408），用于提供表示时钟信号和时钟信号的进一步延迟版本的比较的传感器输出信号。 时钟信号的进一步延迟版本是从第二级联延迟段之后的位于延迟线中的特定延迟段的输出获得的。

    Operating long on-chip buses
    6.
    发明授权
    Operating long on-chip buses 失效
    经营长时间的片上公交车

    公开(公告)号：US07439759B2

    公开(公告)日：2008-10-21

    申请号：US10558145

    申请日：2004-05-17

    申请人： Atul Katoch ,  Manish Garg ,  Evert Seevinck ,  Hendricus Joseph Maria Veendrick

    发明人： Atul Katoch ,  Manish Garg ,  Evert Seevinck ,  Hendricus Joseph Maria Veendrick

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： G06F13/4072

    摘要： As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

    摘要翻译： 随着技术的发展，片上互连变得越来越窄，这种互连的高度并没有随宽度而线性缩放。 这导致与相邻导线的耦合电容的增加，导致更高的串扰。 由于在接收线路时RC响应差，导致性能差，甚至可能导致非常嘈杂的环境中的故障​​。 提出了一种自适应阈值方案，其中接收机切换阈值根据总线线路中检测到的噪声进行调整。 这些噪声水平取决于前端处理（晶体管性能）以及后端处理（金属电阻，电容，宽度和间距）。 因此，电路自动补偿过程变化。

    Flexible CMOS library architecture for leakage power and variability reduction
    7.
    发明授权
    Flexible CMOS library architecture for leakage power and variability reduction 有权
    灵活的CMOS库结构，用于泄漏功率和变异性降低

    公开(公告)号：US08390331B2

    公开(公告)日：2013-03-05

    申请号：US12648880

    申请日：2009-12-29

    申请人： Hendricus Joseph Maria Veendrick ,  Leonardus Hendricus Maria Sevat

    发明人： Hendricus Joseph Maria Veendrick ,  Leonardus Hendricus Maria Sevat

    IPC分类号： H03K19/00 ,  H01L21/82

    CPC分类号： H01L27/11807 ,  H01L27/0207 ,  H01L2027/11831

    摘要： Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.

    摘要翻译： 各种示例性实施例涉及用于集成电路的CMOS晶体管阵列的改进制造。 使用栅极隔离架构的标准单元的规则性增加可能允许进一步减小特征尺寸。 MOSFET可以以大致相等的间距间隔，并且具有增加的沟道长度以减少漏电流。 逻辑门可以设计成具有用于速度的标称通道长度和增加的漏电流减小的通道长度。 进一步的泄漏电流降低可能涉及隔离MOSFET的专用通道长度。 因此，栅极隔离技术与具有以基本上相同间距均匀间隔的延长沟道的MOSFET的组合可以产生用于改进先进CMOS技术节点中的标准单元设计的灵活库架构。

    FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION
    8.
    发明申请
    FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION 有权
    灵活的CMOS图书馆建筑用于泄漏功率和可变性减少

    公开(公告)号：US20110156755A1

    公开(公告)日：2011-06-30

    申请号：US12648880

    申请日：2009-12-29

    申请人： Hendricus Joseph Maria Veendrick ,  Leonardus Hendricus Maria Sevat

    发明人： Hendricus Joseph Maria Veendrick ,  Leonardus Hendricus Maria Sevat

    IPC分类号： H03K19/00 ,  H01L21/82

    CPC分类号： H01L27/11807 ,  H01L27/0207 ,  H01L2027/11831

    摘要： Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.

    摘要翻译： 各种示例性实施例涉及用于集成电路的CMOS晶体管阵列的改进制造。 使用栅极隔离架构的标准单元的规则性增加可能允许进一步减小特征尺寸。 MOSFET可以以大致相等的间距间隔，并且具有增加的沟道长度以减少漏电流。 逻辑门可以设计成具有用于速度的标称通道长度和增加的漏电流减小的通道长度。 进一步的泄漏电流降低可能涉及隔离MOSFET的专用通道长度。 因此，栅极隔离技术与具有以基本上相同间距均匀间隔的延长沟道的MOSFET的组合可以产生用于改进先进CMOS技术节点中的标准单元设计的灵活库架构。

    LITHOGRAPHY ROBUSTNESS MONITOR
    9.
    发明申请
    LITHOGRAPHY ROBUSTNESS MONITOR 审中-公开

    公开(公告)号：US20100308329A1

    公开(公告)日：2010-12-09

    申请号：US12864614

    申请日：2009-01-26

    申请人： Harold Gerardus Pieter Hendrikus Benten ,  Agnese Antonietta Maria Bargagli-Stoffi ,  Hendricus Joseph Maria Veendrick

    发明人： Harold Gerardus Pieter Hendrikus Benten ,  Agnese Antonietta Maria Bargagli-Stoffi ,  Hendricus Joseph Maria Veendrick

    IPC分类号： H01L27/02 ,  H01L21/66 ,  G06F17/50

    CPC分类号： G03F7/70658 ,  H01L22/34

    摘要： The present invention relates to a method and device for monitoring a lithographic process of an integrated circuit. In a first step a design for an integrated circuit is provided. The integrated circuit comprises at least an integrated circuit transistor pair having a gate of a first transistor connected to a gate of a second transistor. The gate of the second transistor is designed such that it has a predetermined overlap with respect to a source and a drain of the second transistor. A detection circuit is connected to the at least an integrated circuit transistor pair for detecting if in operation functionality of the second transistor of each of the at least an integrated circuit transistor pair is one of a transistor and a short circuit. The integrated circuit is then manufactured in dependence upon the desogn. After manufacturing, the detection circuit is used to determine the functionality of the second transistor of each of the at least an integrated circuit transistor pair.

    摘要翻译： 本发明涉及用于监测集成电路的光刻工艺的方法和装置。 在第一步中，提供集成电路的设计。 集成电路至少包括具有连接到第二晶体管的栅极的第一晶体管的栅极的集成电路晶体管对。 第二晶体管的栅极被设计成使得其相对于第二晶体管的源极和漏极具有预定的重叠。 检测电路连接到至少一个集成电路晶体管对，用于检测至少一个集成电路晶体管对中的每一个的第二晶体管的操作功能是晶体管和短路之一。 该集成电路随后依赖于该设备制造。 在制造之后，检测电路用于确定至少一个集成电路晶体管对中的每一个的第二晶体管的功能。

    DLL for period jitter measurement
    10.
    发明授权
    DLL for period jitter measurement 有权
    DLL用于周期抖动测量

    公开(公告)号：US08203368B2

    公开(公告)日：2012-06-19

    申请号：US12995153

    申请日：2009-05-27

    申请人： Marcel J. M. Pelgrom ,  Hendricus Joseph Maria Veendrick ,  Victor Zieren

    发明人： Marcel J. M. Pelgrom ,  Hendricus Joseph Maria Veendrick ,  Victor Zieren

    IPC分类号： H03L7/06

    CPC分类号： G01R31/31709

    摘要： A sensor (400) for sensing jitter in a clock signal has a DLL (402, 310, 312) for locking a clock signal and a delayed version of the clock signal. The sensor comprises a delay line (402) having a first number of cascaded controllable delay segments. The DLL uses a second number of the cascaded delay segments for generating a delay of an average clock period of the clock signal. The second number is smaller than the first number. The sensor also has a comparator (408) for supplying a sensor output signal representative of a comparison of the clock signal and a further delayed version of the clock signal. The further delayed version of the clock signal is obtained from an output of a specific one of the delay segments located in the delay line after the second number of cascaded delay segments.

    摘要翻译： 用于感测时钟信号中的抖动的传感器（400）具有用于锁定时钟信号和时钟信号的延迟版本的DLL（402,310,312）。 传感器包括具有第一数量级联的可控延迟段的延迟线（402）。 DLL使用第二数量的级联延迟段来产生时钟信号的平均时钟周期的延迟。 第二个数字小于第一个数字。 传感器还具有比较器（408），用于提供表示时钟信号和时钟信号的进一步延迟版本的比较的传感器输出信号。 时钟信号的进一步延迟版本是从第二级联延迟段之后的位于延迟线中的特定延迟段的输出获得的。