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    Method and system for efficiently transferring a self-defined non-contiguous message in a one-sided communication model
    2.
    发明申请
    Method and system for efficiently transferring a self-defined non-contiguous message in a one-sided communication model 失效
    用于在单面通信模型中有效传送自定义非连续消息的方法和系统

    公开(公告)号：US20060085518A1

    公开(公告)日：2006-04-20

    申请号：US10965597

    申请日：2004-10-14

    申请人： Robert Blackmore ,  Xin Chen ,  Chulho Kim ,  Rajeev Sivaram ,  Richard Treumann ,  Hanhong Xue

    发明人： Robert Blackmore ,  Xin Chen ,  Chulho Kim ,  Rajeev Sivaram ,  Richard Treumann ,  Hanhong Xue

    IPC分类号： G06F15/16

    CPC分类号： H04L67/10 ,  H04L69/06 ,  H04L69/328

    摘要： A method and system for transferring noncontiguous messages group including assembling a set of data into a series of transmission packets, packaging a description of the layout of the transmission packets into description packets and then places each description packet into a local buffer while maintaining a count of the number of description packets, transfers each description packet into a transmit buffer for transmission to at least one receiving node, identifies the data packets, and forwards each data packet to the transmit buffer for transmission to the at least one receiving node. The receiving node receives the transmission packets, identifies each packet as a description packet or data packet, places the description packets in a local buffer for storage until the description is complete, places each description packet into a user data buffer, stores data packets in a local queue until the description is complete, then transfers the data packets to the user buffer.

    摘要翻译： 一种用于传送不连续消息组的方法和系统，包括将一组数据组合成一系列传输分组，将传输分组的布局的描述打包成描述分组，然后将每个描述分组放置到本地缓冲器中，同时保持计数 描述分组的数量将每个描述分组传送到用于发送到至少一个接收节点的发送缓冲器，识别数据分组，并将每个数据分组转发到发送缓冲器以传输到至少一个接收节点。 接收节点接收传输分组，将每个分组标识为描述分组或数据分组，将描述分组置于本地缓冲区中进行存储，直到描述完成，将每个描述分组放入用户数据缓冲区，将数据分组存储在 本地队列直到描述完成，然后将数据包传送到用户缓冲区。

    Interface method, system, and program product for facilitating layering of a data communications protocol over an active message layer protocol
    4.
    发明授权
    Interface method, system, and program product for facilitating layering of a data communications protocol over an active message layer protocol 失效
    接口方法，系统和程序产品，用于促进通过活动消息层协议分层数据通信协议

    公开(公告)号：US07536468B2

    公开(公告)日：2009-05-19

    申请号：US10875471

    申请日：2004-06-24

    申请人： Robert S. Blackmore ,  Xin Chen ,  Scott D. Epter ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    发明人： Robert S. Blackmore ,  Xin Chen ,  Scott D. Epter ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    IPC分类号： G06F15/16 ,  H04L12/28

    CPC分类号： H04L51/18 ,  H04L69/22

    摘要： A protocol interface is provided for an active message protocol of a computing environment and a client process employing the active message protocol. The protocol interface includes an interface to a header handler function associated with the client process. The interface to the header handler function has parameters to be passed by and a parameter to be returned to the active message protocol when processing a message received through the active message protocol. The parameters to be passed include current message state information and current message type information for the received message. These parameters facilitate message-specific decisions by the header handler function about processing data of the message by the active message protocol. The parameter to be returned to the active message protocol instructs the active message protocol how to process the received message other than just where to store the message.

    摘要翻译： 为计算环境的活动消息协议和采用活动消息协议的客户端进程提供协议接口。 协议接口包括与客户端进程相关联的报头处理函数的接口。 在处理通过活动消息协议接收的消息时，头处理程序函数的接口具有要传递的参数和要返回到活动消息协议的参数。 要传递的参数包括接收到的消息的当前消息状态信息和当前消息类型信息。 这些参数有助于报头处理函数关于通过活动消息协议处理消息的数据的消息特定决定。 要返回到活动消息协议的参数指示活动消息协议如何处理接收到的消息，而不仅仅是存储消息的位置。

    EFFICIENT PIPELINING OF RDMA FOR COMMUNICATIONS
    5.
    发明申请
    EFFICIENT PIPELINING OF RDMA FOR COMMUNICATIONS 审中-公开
    RDMA通信的有效管道

    公开(公告)号：US20110078410A1

    公开(公告)日：2011-03-31

    申请号：US11457921

    申请日：2006-07-17

    申请人： Robert S. Blackmore ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Richard R. Treumann ,  Hanhong Xue

    发明人： Robert S. Blackmore ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Richard R. Treumann ,  Hanhong Xue

    IPC分类号： G06F12/00 ,  G06F15/76 ,  G06F9/02

    CPC分类号： G06F15/17375

    摘要： Disclosed are a method of and system for multiple party communications in a processing system including multiple processing subsystems. Each of the processing subsystems includes a central processing unit and one or more network adapters for connecting said each processing subsystem to the other processing subsystems. A multitude of nodes are established or created, and each of these nodes is associated with one of the processing subsystems. A first aspect of the invention involves pipelined communication using RDMA among three nodes, where the first node breaks up a large communication into multiple parts and sends these parts one after the other to the second node using RDMA, and the second node in turn absorbs and forwards each of these parts to a third node before all parts of the communication arrive from the first node.

    摘要翻译： 公开了一种包括多个处理子系统的处理系统中的多方通信的方法和系统。 每个处理子系统包括中央处理单元和用于将所述每个处理子系统连接到其他处理子系统的一个或多个网络适配器。 建立或创建多个节点，并且这些节点中的每一个都与处理子系统之一相关联。 本发明的第一方面涉及在三个节点之间使用RDMA的流水线通信，其中第一节点将大型通信分解成多个部分，并且使用RDMA将这些部分一个接一个地发送到第二节点，并且第二节点依次吸收和 在通信的所有部分从第一节点到达之前，将这些部分中的每一个转发到第三节点。

    System and method for intelligent software-controlled cache injection
    6.
    发明授权
    System and method for intelligent software-controlled cache injection 失效
    用于智能软件控制缓存注入的系统和方法

    公开(公告)号：US07774554B2

    公开(公告)日：2010-08-10

    申请号：US11676745

    申请日：2007-02-20

    申请人： Piyush Chaudhary ,  Rama K. Govindaraju ,  Jay Robert Herring ,  Peter Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    发明人： Piyush Chaudhary ,  Rama K. Govindaraju ,  Jay Robert Herring ,  Peter Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F12/0817

    摘要： A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be written to a memory location associated with the target processor is found in a processor cache of the target processor. If it is determined that the memory address is found in a target processor's cache, the data will be directly written to that cache at the same time that the data is being provided to a location in main memory.

    摘要翻译： 当处理器先前已经对数据感兴趣时，提供将重要数据直接注入处理器的高速缓存位置的系统和方法。 目标处理器上的存储器子系统将确定是否在目标处理器的处理器高速缓存中找到要写入到与目标处理器相关联的存储器位置的数据的存储器地址。 如果确定在目标处理器的高速缓存中找到存储器地址，则在将数据提供给主存储器中的位置的同时，数据将被直接写入该高速缓存。

    Method and system for efficiently transferring a self-defined non-contiguous message in a one-sided communication model
    7.
    发明授权
    Method and system for efficiently transferring a self-defined non-contiguous message in a one-sided communication model 失效
    用于在单面通信模型中有效传送自定义非连续消息的方法和系统

    公开(公告)号：US07454491B2

    公开(公告)日：2008-11-18

    申请号：US10965597

    申请日：2004-10-14

    申请人： Robert S. Blackmore ,  Xin Amy Chen ,  Chulho Kim ,  Rajeev Sivaram ,  Richard R. Treumann ,  Hanhong Xue

    发明人： Robert S. Blackmore ,  Xin Amy Chen ,  Chulho Kim ,  Rajeev Sivaram ,  Richard R. Treumann ,  Hanhong Xue

    IPC分类号： G06F15/16

    CPC分类号： H04L67/10 ,  H04L69/06 ,  H04L69/328

    摘要： A method and system for transferring noncontiguous messages group including assembling a set of data into a series of transmission packets, packaging a description of the layout of the transmission packets into description packets and then places each description packet into a local buffer while maintaining a count of the number of description packets, transfers each description packet into a transmit buffer for transmission to at least one receiving node, identifies the data packets, and forwards each data packet to the transmit buffer for transmission to the at least one receiving node. The receiving node receives the transmission packets, identifies each packet as a description packet or data packet, places the description packets in a local buffer for storage until the description is complete, places each description packet into a user data buffer, stores data packets in a local queue until the description is complete, then transfers the data packets to the user buffer.

    摘要翻译： 一种用于传送不连续消息组的方法和系统，包括将一组数据组合成一系列传输分组，将传输分组的布局的描述打包成描述分组，然后将每个描述分组放置到本地缓冲器中，同时保持计数 描述分组的数量将每个描述分组传送到用于发送到至少一个接收节点的发送缓冲器，识别数据分组，并将每个数据分组转发到发送缓冲器以传输到至少一个接收节点。 接收节点接收传输分组，将每个分组标识为描述分组或数据分组，将描述分组置于本地缓冲区中进行存储，直到描述完成，将每个描述分组放入用户数据缓冲区，将数据分组存储在 本地队列直到描述完成，然后将数据包传送到用户缓冲区。

    System and Method for Intelligent Software-Controlled Cache Injection
    9.
    发明申请
    System and Method for Intelligent Software-Controlled Cache Injection 失效
    智能软件控制缓存注入系统与方法

    公开(公告)号：US20080201532A1

    公开(公告)日：2008-08-21

    申请号：US11676745

    申请日：2007-02-20

    申请人： Piyush Chaudhary ,  Rama K. Govindaraju ,  Jay Robert Herring ,  Peter Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    发明人： Piyush Chaudhary ,  Rama K. Govindaraju ,  Jay Robert Herring ,  Peter Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0817

    摘要： A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be written to a memory location associated with the target processor is found in a processor cache of the target processor. If it is determined that the memory address is found in a target processor's cache, the data will be directly written to that cache at the same time that the data is being provided to a location in main memory.

    摘要翻译： 当处理器先前已经对数据感兴趣时，提供将重要数据直接注入处理器的高速缓存位置的系统和方法。 目标处理器上的存储器子系统将确定是否在目标处理器的处理器高速缓存中找到要写入到与目标处理器相关联的存储器位置的数据的存储器地址。 如果确定在目标处理器的高速缓存中找到存储器地址，则在将数据提供给主存储器中的位置的同时，数据将被直接写入该高速缓存。