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公开(公告)号：US07447965B2
公开(公告)日：2008-11-04
申请号：US11121164
申请日：2005-05-03
申请人： Robert D. Brink , James Walter Hofmann, Jr. , Max J. Olsen , Gary E. Schiessler , Lane A. Smith
发明人： Robert D. Brink , James Walter Hofmann, Jr. , Max J. Olsen , Gary E. Schiessler , Lane A. Smith
CPC分类号： H04L1/244
摘要： Communications equipment can be tested using a test pattern encapsulated within a frame, and offsetting the test pattern in each successive frame. In equipment having a number of data latches receiving serial input, the introduction of the offset allows each latch, over time, to be exposed to the same pattern as the other latches. That is, the latches “see” different portions of the pattern at a given time, but over time, each can be exposed to the full pattern. Otherwise, each latch would “see” its own static pattern, different from the other latches, but the same over time with respect to itself. The offset can enhance diagnostic capabilities of the test pattern.
摘要翻译： 可以使用封装在帧内的测试图案来测试通信设备，并且在每个连续帧中抵消测试模式。 在具有接收串行输入的多个数据锁存器的设备中，引入偏移允许每个锁存器随时间暴露于与其他锁存器相同的模式。 也就是说，锁定器在给定时间“看到”图案的不同部分，但是随着时间的推移，每个可以暴露于完整图案。 否则，每个锁存器将“看到”其自己的静态模式，与其他锁存器不同，但是相对于自身而言随着时间的推移相同。 该偏移可以增强测试图案的诊断功能。
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公开(公告)号：US07272756B2
公开(公告)日：2007-09-18
申请号：US11121152
申请日：2005-05-03
申请人： Robert D. Brink , James Walter Hofmann, Jr. , Max J. Olsen , Gary E. Schiessler , Lane A. Smith
发明人： Robert D. Brink , James Walter Hofmann, Jr. , Max J. Olsen , Gary E. Schiessler , Lane A. Smith
IPC分类号： G01R31/28
摘要： Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or shortened consecutive identical digit (CID) portions, or that have lengthened or shortened pseudo random bit sequence (PRBS) portions. In some cases, PRBS polynomials are not re-seeded after each CID. Further, different order polynomials can be employed for different applications. Exemplary applications can include test equipment and built-in self-test capability for integrated circuits.
摘要翻译： 通信设备可以使用与标准测试模式相比修改的测试模式进行测试，并且比标准测试模式更具有潜力。 可以采用具有延长或缩短连续相同数字（CID）部分或具有延长或缩短的伪随机位序列（PRBS）部分的测试模式。 在某些情况下，在每个CID之后，PRBS多项式不再重播。 此外，不同的阶多项式可以用于不同的应用。 示例性应用可以包括测试设备和用于集成电路的内置自检能力。
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公开(公告)号：US08559580B2
公开(公告)日：2013-10-15
申请号：US12494771
申请日：2009-06-30
CPC分类号： H04L1/20
摘要： Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.
摘要翻译： 公开了用于眼图生成的异步校准的技术。 例如，用于校准与接收信号相关联的用于生成数据眼的处理的方法包括以下步骤。 使用第一数据锁存器和漫游锁存器，以第一单位间隔获得接收信号的样本。 通过比较使用第一数据锁存器获得的至少一个样本和使用漫游锁存器获得的至少一个样本，在第一数据锁存器和漫游锁存器之间确定延迟偏移，其中由比较确定的延迟偏移用于校准 用于产生与接收信号相关联的数据眼的过程。 可以对第二数据锁存器进行类似的比较，并用于校准该过程。 该方法能够找到每个数据锁存器相对于漫游锁存器的准确位置，以提高数字接收机中数据解码的准确度，即提供接收机优化。
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公开(公告)号：US07489754B2
公开(公告)日：2009-02-10
申请号：US11053365
申请日：2005-02-08
申请人： Xingdong Dai , Max J. Olsen , Lane A. Smith
发明人： Xingdong Dai , Max J. Olsen , Lane A. Smith
IPC分类号： H04L7/02
摘要： A frequency-lock detector (FLD) adapted to register more than one target count per period of a target clock signal to generate a count value related to a frequency difference between the target clock signal and a reference clock signal. In various embodiments of the invention, this count registration is implemented by multiplying the target clock signal, discerning two or more phases of a signal, and/or organizing a count pipeline. In a representative embodiment, an FLD of the invention has a counter circuit and a control circuit. The counter circuit has (i) a frequency multiplier adapted to multiply the frequency of the target clock signal to generate a multiplied signal, (ii) two target counters adapted to register counts based on occurrences of two different phases of the accelerated signal to generate two auxiliary numbers, and (iii) a multiplexer adapted to select an appropriate one of the auxiliary numbers as the count value related to the frequency difference. The control circuit has a reference counter adapted to control, based on the reference clock signal, the count registration in the target counters and the value selection in the multiplexer.
摘要翻译： 一种频率锁定检测器（FLD），适于在目标时钟信号的每个周期寄存多于一个目标计数，以产生与目标时钟信号和参考时钟信号之间的频率差相关的计数值。 在本发明的各种实施例中，通过对目标时钟信号进行乘法，辨别信号的两个或多个相位和/或组织计数流水线来实现该计数登记。 在代表性的实施例中，本发明的FLD具有计数器电路和控制电路。 计数器电路具有（i）适于乘以目标时钟信号的频率以产生相乘的信号的倍频器，（ii）适于基于加速信号的两个不同相位的出现来寄存计数的两个目标计数器，以产生两个 辅助号码，以及（iii）适合于选择适当的一个辅助号码作为与频率差有关的计数值的多路复用器。 该控制电路具有一个参考计数器，该参考计数器适于基于参考时钟信号控制目标计数器中的计数注册和多路复用器中的值选择。
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公开(公告)号：US20100329318A1
公开(公告)日：2010-12-30
申请号：US12494771
申请日：2009-06-30
IPC分类号： H04B17/00
CPC分类号： H04L1/20
摘要： Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.
摘要翻译： 公开了用于眼图生成的异步校准的技术。 例如，用于校准与接收信号相关联的用于生成数据眼的处理的方法包括以下步骤。 使用第一数据锁存器和漫游锁存器，以第一单位间隔获得接收信号的样本。 通过比较使用第一数据锁存器获得的至少一个样本和使用漫游锁存器获得的至少一个样本，在第一数据锁存器和漫游锁存器之间确定延迟偏移，其中由比较确定的延迟偏移用于校准 用于产生与接收信号相关联的数据眼的过程。 可以对第二数据锁存器进行类似的比较，并用于校准该过程。 该方法能够找到每个数据锁存器相对于漫游锁存器的准确位置，以提高数字接收机中数据解码的准确度，即提供接收机优化。
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6.发明申请Multi-Band Gain Adaptation for Receiver Equalization Using Approximate Frequency Separation 审中-公开使用近似频率分离的接收机均衡的多频带增益适配公开(公告)号：US20100290515A1
公开(公告)日：2010-11-18
申请号：US12467507
申请日：2009-05-18
申请人： Xingdong Dai , Wenyi Jin , Max J. Olsen , Geoffrey Zhang
发明人： Xingdong Dai , Wenyi Jin , Max J. Olsen , Geoffrey Zhang
IPC分类号： H03H7/40
CPC分类号： H04L25/03057
摘要： A receiver comprises equalization circuitry implementing at least first and second gain adaptation loops associated with respective first and second frequency bands. The equalization circuitry in one aspect is operative to identify a pattern in a portion of a received serial data stream, and to perform gain adaptation for the receiver utilizing a particular one of the gain adaptation loops responsive to the identified pattern. For example, the gain adaptation may be performed utilizing a low frequency gain adaptation loop if the detected pattern is of a first type generally associated with a low frequency band, and may be performed utilizing a high frequency gain adaptation loop if the detected pattern is of a second type generally associated with a high frequency band. In other aspects, the first and second gain adaptation loops may be activated in a particular serial order or in parallel.
摘要翻译： 接收机包括实现与相应的第一和第二频带相关联的至少第一和第二增益适配环路的均衡电路。 一个方面中的均衡电路用于识别接收的串行数据流的一部分中的模式，并且响应于所识别的模式，利用增益适配环路中的特定一个对接收机执行增益适配。 例如，如果检测到的模式是通常与低频带相关联的第一类型，则可以利用低频增益适配环来执行增益适配，并且如果检测到的模式是 通常与高频带相关联的第二类型。 在其他方面，可以以特定的串行顺序或并行地激活第一和第二增益适配环。
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公开(公告)号：US08611406B2
公开(公告)日：2013-12-17
申请号：US12494805
申请日：2009-06-30
申请人： Xingdong Dai , Max J. Olsen , Scott A. Werner , Geoffrey Zhang
发明人： Xingdong Dai , Max J. Olsen , Scott A. Werner , Geoffrey Zhang
CPC分类号： G01R31/3171
摘要： Communication system optimization using a soft receiver masking technique is disclosed. For example, a method for testing a communication device comprises obtaining a software representation of a receiver portion of a given communication device. A data signal received from a transmitter through a given link channel is then processed, wherein the processing step is performed using the software representation of the receiver portion of the communication device. An output signal is caused to be generated by the software representation of the receiver portion. An eye mask test is then applied to the output signal. Based on a result of the eye mask test, one or more parameters of the transmitter may be adjusted.
摘要翻译： 公开了使用软接收机屏蔽技术的通信系统优化。 例如，用于测试通信设备的方法包括获得给定通信设备的接收机部分的软件表示。 然后处理从发射机通过给定链路信道接收的数据信号，其中使用通信设备的接收机部分的软件表示来执行处理步骤。 由接收器部分的软件表示产生输出信号。 然后将眼罩测试应用于输出信号。 基于眼罩测试的结果，可以调整发射器的一个或多个参数。
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公开(公告)号：US07882404B2
公开(公告)日：2011-02-01
申请号：US11935759
申请日：2007-11-06
申请人： Xingdong Dai , Geoffrey Zhang , Max J. Olsen
发明人： Xingdong Dai , Geoffrey Zhang , Max J. Olsen
IPC分类号： G01R31/28
CPC分类号： H04L25/03343 , H04L25/0264 , H04L25/0286 , H04L25/03057 , H04L25/4923
摘要： The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitter pre-emphasis circuit (TPXE) that pre-emphasizes a transmitted signal and a receiver equalization circuit (RXEQ) that equalizes a received signal. The TPXE includes coefficients that are dynamically programmable.
摘要翻译： 本发明实现了使用串行器/解串器（SerDes）内的组件来模拟背板的效果以方便SerDes的自动测试设备（ATE）测试的方法和装置。 SerDes包括预先强调发射信号的发射机预加重电路（TPXE）和均衡接收信号的接收机均衡电路（RXEQ）。 TPXE包括可动态编程的系数。
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公开(公告)号：US4744692A
公开(公告)日：1988-05-17
申请号：US99802
申请日：1987-09-22
CPC分类号： F16B2/14 , B25G3/36 , F16B2/10 , Y10T403/7069 , Y10T403/76
摘要： This invention relates to a clamping device for removably attaching a tool element to a bracket element wherein a bracket element is disposed in a groove in the tool and a clamping member is disposed in said groove and in engagement with a clamping face of the bracket and a wall of the groove and with the clamping member having pivot means engaging the bracket and about which the clamping member rotates.
摘要翻译： 本发明涉及一种用于将工具元件可拆卸地安装到支架元件的夹紧装置，其中支架元件设置在工具中的凹槽中，夹紧件设置在所述槽中并与支架的夹紧面接合， 所述槽的壁和所述夹紧构件具有接合所述支架的枢转装置，并且所述夹紧构件围绕所述枢转装置旋转。
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10.发明授权SerDes jitter tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit 有权SerDes抖动容限BIST在增强扩频时钟发生电路的生产环回测试中公开(公告)号：US08958515B2
公开(公告)日：2015-02-17
申请号：US13096454
申请日：2011-04-28
申请人： Yi Cai , Ivan Chan , Liming Fang , Max J. Olsen
发明人： Yi Cai , Ivan Chan , Liming Fang , Max J. Olsen
CPC分类号： G06G7/16 , G01R31/31709 , H04B15/04 , H04L7/00
摘要： A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local oscillator signal to output a first mixer output. The second mixer is configured to mix the fixed frequency clock signal with the quadrature local oscillator signal to output a second mixer output. An adder is configured to add the first and second mixer outputs to produce a frequency-modulated clock signal with a frequency that is about the sum of the fixed frequency and the local oscillator frequency and includes a periodic jitter.
摘要翻译： 用于可控制地产生串行数据流中的抖动的系统包括频率发生器和第一和第二混频器。 频率发生器被配置为输出具有至少约5MHz的本地振荡器频率的同相和正交本地振荡器信号。 本地振荡器频率在可选择的最小频率和可选择的最大频率之间变化。 第一混频器被配置为将固定频率时钟信号与同相本地振荡器信号混频以输出第一混频器输出。 第二混频器被配置为将固定频率时钟信号与正交本地振荡器信号混频以输出第二混频器输出。 加法器被配置为添加第一和第二混频器输出以产生频率约为固定频率和本地振荡器频率之和的频率调制时钟信号，并且包括周期性抖动。
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